- u8 modereg;
-
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10) {
- switch (edata->phy_interface) {
- case PHY_INTERFACE_MODE_MII:
- case PHY_INTERFACE_MODE_GMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- break;
- case PHY_INTERFACE_MODE_RMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- break;
- case PHY_INTERFACE_MODE_RGMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- break;
- default:
- dev_err(dev, "Unsupported PHY mode\n");
- return -EINVAL;
- }
-
- ret = reset_get_bulk(dev, &reset_bulk);
- if (ret) {
- dev_err(dev, "Failed to get reset: %d\n", ret);
- return ret;
- }
-
- reset_assert_bulk(&reset_bulk);
-
- clrsetbits_le32(pdata->phy_intf,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
- modereg);
-
- reset_release_bulk(&reset_bulk);
+ u32 modereg;
+ u32 modemask;
+
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ break;
+ default:
+ dev_err(dev, "Unsupported PHY mode\n");
+ return -EINVAL;