- /* Changes to cpc0_sys0 and cpc0_sys1 require chip
- * reset.
- */
- mtdcr( cntrl0, mfdcr(cntrl0) | 0x80000000 ); /* Set SWE */
- mtdcr( cpc0_sys0, sys0 );
- mtdcr( cpc0_sys1, sys1 );
- mtdcr( cntrl0, mfdcr(cntrl0) & ~0x80000000 ); /* Clr SWE */
- mtspr( dbcr0, 0x20000000); /* Reset the chip */
-
- return 1;
+ /* Changes to cpc0_sys0 and cpc0_sys1 require chip
+ * reset.
+ */
+ mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
+ mtdcr (cpc0_sys0, sys0);
+ mtdcr (cpc0_sys1, sys1);
+ mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
+ mtspr (dbcr0, 0x20000000); /* Reset the chip */
+
+ return 1;