am437x: Add am437x_gp_evm_defconfig using CONFIG_DM
authorMugunthan V N <mugunthanvnm@ti.com>
Mon, 28 Sep 2015 10:47:51 +0000 (16:17 +0530)
committerTom Rini <trini@konsulko.com>
Thu, 22 Oct 2015 18:44:00 +0000 (14:44 -0400)
Import various DT files for am4372, an43xx pinctrl and
am437x-gp-evm from Linux Kernel v4.2
Add config file for this board, enable DM, DM_GPIO, DM_SERIAL
and DM_MMC.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/dts/Makefile
arch/arm/dts/am4372.dtsi [new file with mode: 0644]
arch/arm/dts/am437x-gp-evm.dts [new file with mode: 0644]
arch/arm/dts/am43xx-clocks.dtsi [new file with mode: 0644]
configs/am437x_gp_evm_defconfig [new file with mode: 0644]
include/dt-bindings/pinctrl/am43xx.h [new file with mode: 0644]
include/dt-bindings/pwm/pwm.h [new file with mode: 0644]

index 42aea29..c663973 100644 (file)
@@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
        zynq-zc770-xm012.dtb \
        zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
        zynq-zc770-xm012.dtb \
        zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
+dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=                          \
        socfpga_arria5_socdk.dtb                        \
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=                          \
        socfpga_arria5_socdk.dtb                        \
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
new file mode 100644 (file)
index 0000000..ade28c7
--- /dev/null
@@ -0,0 +1,999 @@
+/*
+ * Device Tree Source for AM4372 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+       compatible = "ti,am4372", "ti,am43";
+       interrupt-parent = <&wakeupgen>;
+
+
+       aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               serial0 = &uart0;
+               ethernet0 = &cpsw_emac0;
+               ethernet1 = &cpsw_emac1;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu: cpu@0 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <0>;
+
+                       clocks = <&dpll_mpu_ck>;
+                       clock-names = "cpu";
+
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
+               };
+       };
+
+       gic: interrupt-controller@48241000 {
+               compatible = "arm,cortex-a9-gic";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               reg = <0x48241000 0x1000>,
+                     <0x48240100 0x0100>;
+               interrupt-parent = <&gic>;
+       };
+
+       wakeupgen: interrupt-controller@48281000 {
+               compatible = "ti,omap4-wugen-mpu";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               reg = <0x48281000 0x1000>;
+               interrupt-parent = <&gic>;
+       };
+
+       l2-cache-controller@48242000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x48242000 0x1000>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
+       ocp {
+               compatible = "ti,am4372-l3-noc", "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+               ti,hwmods = "l3_main";
+               reg = <0x44000000 0x400000
+                      0x44800000 0x400000>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+               l4_wkup: l4_wkup@44c00000 {
+                       compatible = "ti,am4-l4-wkup", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0 0x44c00000 0x287000>;
+
+                       prcm: prcm@1f0000 {
+                               compatible = "ti,am4-prcm";
+                               reg = <0x1f0000 0x11000>;
+
+                               prcm_clocks: clocks {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                               };
+
+                               prcm_clockdomains: clockdomains {
+                               };
+                       };
+
+                       scm: scm@210000 {
+                               compatible = "ti,am4-scm", "simple-bus";
+                               reg = <0x210000 0x4000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0 0x210000 0x4000>;
+
+                               am43xx_pinmux: pinmux@800 {
+                                       compatible = "ti,am437-padconf",
+                                                    "pinctrl-single";
+                                       reg = <0x800 0x31c>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       #interrupt-cells = <1>;
+                                       interrupt-controller;
+                                       pinctrl-single,register-width = <32>;
+                                       pinctrl-single,function-mask = <0xffffffff>;
+                               };
+
+                               scm_conf: scm_conf@0 {
+                                       compatible = "syscon";
+                                       reg = <0x0 0x800>;
+                                       #address-cells = <1>;
+                                       #size-cells = <1>;
+
+                                       scm_clocks: clocks {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                       };
+                               };
+
+                               scm_clockdomains: clockdomains {
+                               };
+                       };
+               };
+
+               emif: emif@4c000000 {
+                       compatible = "ti,emif-am4372";
+                       reg = <0x4c000000 0x1000000>;
+                       ti,hwmods = "emif";
+               };
+
+               edma: edma@49000000 {
+                       compatible = "ti,edma3";
+                       ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+                       reg =   <0x49000000 0x10000>,
+                               <0x44e10f90 0x10>;
+                       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+               };
+
+               uart0: serial@44e09000 {
+                       compatible = "ti,am4372-uart","ti,omap2-uart";
+                       reg = <0x44e09000 0x2000>;
+                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "uart1";
+               };
+
+               uart1: serial@48022000 {
+                       compatible = "ti,am4372-uart","ti,omap2-uart";
+                       reg = <0x48022000 0x2000>;
+                       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "uart2";
+                       status = "disabled";
+               };
+
+               uart2: serial@48024000 {
+                       compatible = "ti,am4372-uart","ti,omap2-uart";
+                       reg = <0x48024000 0x2000>;
+                       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "uart3";
+                       status = "disabled";
+               };
+
+               uart3: serial@481a6000 {
+                       compatible = "ti,am4372-uart","ti,omap2-uart";
+                       reg = <0x481a6000 0x2000>;
+                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "uart4";
+                       status = "disabled";
+               };
+
+               uart4: serial@481a8000 {
+                       compatible = "ti,am4372-uart","ti,omap2-uart";
+                       reg = <0x481a8000 0x2000>;
+                       interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "uart5";
+                       status = "disabled";
+               };
+
+               uart5: serial@481aa000 {
+                       compatible = "ti,am4372-uart","ti,omap2-uart";
+                       reg = <0x481aa000 0x2000>;
+                       interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "uart6";
+                       status = "disabled";
+               };
+
+               mailbox: mailbox@480C8000 {
+                       compatible = "ti,omap4-mailbox";
+                       reg = <0x480C8000 0x200>;
+                       interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "mailbox";
+                       #mbox-cells = <1>;
+                       ti,mbox-num-users = <4>;
+                       ti,mbox-num-fifos = <8>;
+                       mbox_wkupm3: wkup_m3 {
+                               ti,mbox-tx = <0 0 0>;
+                               ti,mbox-rx = <0 0 3>;
+                       };
+               };
+
+               timer1: timer@44e31000 {
+                       compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
+                       reg = <0x44e31000 0x400>;
+                       interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,timer-alwon;
+                       ti,hwmods = "timer1";
+               };
+
+               timer2: timer@48040000  {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x48040000  0x400>;
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "timer2";
+               };
+
+               timer3: timer@48042000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x48042000 0x400>;
+                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "timer3";
+                       status = "disabled";
+               };
+
+               timer4: timer@48044000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x48044000 0x400>;
+                       interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,timer-pwm;
+                       ti,hwmods = "timer4";
+                       status = "disabled";
+               };
+
+               timer5: timer@48046000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x48046000 0x400>;
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,timer-pwm;
+                       ti,hwmods = "timer5";
+                       status = "disabled";
+               };
+
+               timer6: timer@48048000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x48048000 0x400>;
+                       interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,timer-pwm;
+                       ti,hwmods = "timer6";
+                       status = "disabled";
+               };
+
+               timer7: timer@4804a000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x4804a000 0x400>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,timer-pwm;
+                       ti,hwmods = "timer7";
+                       status = "disabled";
+               };
+
+               timer8: timer@481c1000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x481c1000 0x400>;
+                       interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "timer8";
+                       status = "disabled";
+               };
+
+               timer9: timer@4833d000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x4833d000 0x400>;
+                       interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "timer9";
+                       status = "disabled";
+               };
+
+               timer10: timer@4833f000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x4833f000 0x400>;
+                       interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "timer10";
+                       status = "disabled";
+               };
+
+               timer11: timer@48341000 {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x48341000 0x400>;
+                       interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "timer11";
+                       status = "disabled";
+               };
+
+               counter32k: counter@44e86000 {
+                       compatible = "ti,am4372-counter32k","ti,omap-counter32k";
+                       reg = <0x44e86000 0x40>;
+                       ti,hwmods = "counter_32k";
+               };
+
+               rtc: rtc@44e3e000 {
+                       compatible = "ti,am4372-rtc","ti,da830-rtc";
+                       reg = <0x44e3e000 0x1000>;
+                       interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "rtc";
+                       status = "disabled";
+               };
+
+               wdt: wdt@44e35000 {
+                       compatible = "ti,am4372-wdt","ti,omap3-wdt";
+                       reg = <0x44e35000 0x1000>;
+                       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "wd_timer2";
+               };
+
+               gpio0: gpio@44e07000 {
+                       compatible = "ti,am4372-gpio","ti,omap4-gpio";
+                       reg = <0x44e07000 0x1000>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       ti,hwmods = "gpio1";
+                       status = "disabled";
+               };
+
+               gpio1: gpio@4804c000 {
+                       compatible = "ti,am4372-gpio","ti,omap4-gpio";
+                       reg = <0x4804c000 0x1000>;
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       ti,hwmods = "gpio2";
+                       status = "disabled";
+               };
+
+               gpio2: gpio@481ac000 {
+                       compatible = "ti,am4372-gpio","ti,omap4-gpio";
+                       reg = <0x481ac000 0x1000>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       ti,hwmods = "gpio3";
+                       status = "disabled";
+               };
+
+               gpio3: gpio@481ae000 {
+                       compatible = "ti,am4372-gpio","ti,omap4-gpio";
+                       reg = <0x481ae000 0x1000>;
+                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       ti,hwmods = "gpio4";
+                       status = "disabled";
+               };
+
+               gpio4: gpio@48320000 {
+                       compatible = "ti,am4372-gpio","ti,omap4-gpio";
+                       reg = <0x48320000 0x1000>;
+                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       ti,hwmods = "gpio5";
+                       status = "disabled";
+               };
+
+               gpio5: gpio@48322000 {
+                       compatible = "ti,am4372-gpio","ti,omap4-gpio";
+                       reg = <0x48322000 0x1000>;
+                       interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       ti,hwmods = "gpio6";
+                       status = "disabled";
+               };
+
+               hwspinlock: spinlock@480ca000 {
+                       compatible = "ti,omap4-hwspinlock";
+                       reg = <0x480ca000 0x1000>;
+                       ti,hwmods = "spinlock";
+                       #hwlock-cells = <1>;
+               };
+
+               i2c0: i2c@44e0b000 {
+                       compatible = "ti,am4372-i2c","ti,omap4-i2c";
+                       reg = <0x44e0b000 0x1000>;
+                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "i2c1";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@4802a000 {
+                       compatible = "ti,am4372-i2c","ti,omap4-i2c";
+                       reg = <0x4802a000 0x1000>;
+                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "i2c2";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@4819c000 {
+                       compatible = "ti,am4372-i2c","ti,omap4-i2c";
+                       reg = <0x4819c000 0x1000>;
+                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "i2c3";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi0: spi@48030000 {
+                       compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+                       reg = <0x48030000 0x400>;
+                       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "spi0";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               mmc1: mmc@48060000 {
+                       compatible = "ti,omap4-hsmmc";
+                       reg = <0x48060000 0x1000>;
+                       ti,hwmods = "mmc1";
+                       ti,dual-volt;
+                       ti,needs-special-reset;
+                       dmas = <&edma 24
+                               &edma 25>;
+                       dma-names = "tx", "rx";
+                       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               mmc2: mmc@481d8000 {
+                       compatible = "ti,omap4-hsmmc";
+                       reg = <0x481d8000 0x1000>;
+                       ti,hwmods = "mmc2";
+                       ti,needs-special-reset;
+                       dmas = <&edma 2
+                               &edma 3>;
+                       dma-names = "tx", "rx";
+                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               mmc3: mmc@47810000 {
+                       compatible = "ti,omap4-hsmmc";
+                       reg = <0x47810000 0x1000>;
+                       ti,hwmods = "mmc3";
+                       ti,needs-special-reset;
+                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               spi1: spi@481a0000 {
+                       compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+                       reg = <0x481a0000 0x400>;
+                       interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "spi1";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi2: spi@481a2000 {
+                       compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+                       reg = <0x481a2000 0x400>;
+                       interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "spi2";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi3: spi@481a4000 {
+                       compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+                       reg = <0x481a4000 0x400>;
+                       interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "spi3";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi4: spi@48345000 {
+                       compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
+                       reg = <0x48345000 0x400>;
+                       interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "spi4";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               mac: ethernet@4a100000 {
+                       compatible = "ti,am4372-cpsw","ti,cpsw";
+                       reg = <0x4a100000 0x800
+                              0x4a101200 0x100>;
+                       interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
+                                     GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ti,hwmods = "cpgmac0";
+                       clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
+                       clock-names = "fck", "cpts";
+                       status = "disabled";
+                       cpdma_channels = <8>;
+                       ale_entries = <1024>;
+                       bd_ram_size = <0x2000>;
+                       no_bd_ram = <0>;
+                       rx_descs = <64>;
+                       mac_control = <0x20>;
+                       slaves = <2>;
+                       active_slave = <0>;
+                       cpts_clock_mult = <0x80000000>;
+                       cpts_clock_shift = <29>;
+                       ranges;
+
+                       davinci_mdio: mdio@4a101000 {
+                               compatible = "ti,am4372-mdio","ti,davinci_mdio";
+                               reg = <0x4a101000 0x100>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               ti,hwmods = "davinci_mdio";
+                               bus_freq = <1000000>;
+                               status = "disabled";
+                       };
+
+                       cpsw_emac0: slave@4a100200 {
+                               /* Filled in by U-Boot */
+                               mac-address = [ 00 00 00 00 00 00 ];
+                       };
+
+                       cpsw_emac1: slave@4a100300 {
+                               /* Filled in by U-Boot */
+                               mac-address = [ 00 00 00 00 00 00 ];
+                       };
+
+                       phy_sel: cpsw-phy-sel@44e10650 {
+                               compatible = "ti,am43xx-cpsw-phy-sel";
+                               reg= <0x44e10650 0x4>;
+                               reg-names = "gmii-sel";
+                       };
+               };
+
+               epwmss0: epwmss@48300000 {
+                       compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+                       reg = <0x48300000 0x10>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "epwmss0";
+                       status = "disabled";
+
+                       ecap0: ecap@48300100 {
+                               compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48300100 0x80>;
+                               ti,hwmods = "ecap0";
+                               status = "disabled";
+                       };
+
+                       ehrpwm0: ehrpwm@48300200 {
+                               compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48300200 0x80>;
+                               ti,hwmods = "ehrpwm0";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss1: epwmss@48302000 {
+                       compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+                       reg = <0x48302000 0x10>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "epwmss1";
+                       status = "disabled";
+
+                       ecap1: ecap@48302100 {
+                               compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48302100 0x80>;
+                               ti,hwmods = "ecap1";
+                               status = "disabled";
+                       };
+
+                       ehrpwm1: ehrpwm@48302200 {
+                               compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48302200 0x80>;
+                               ti,hwmods = "ehrpwm1";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss2: epwmss@48304000 {
+                       compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+                       reg = <0x48304000 0x10>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "epwmss2";
+                       status = "disabled";
+
+                       ecap2: ecap@48304100 {
+                               compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                               #pwm-cells = <3>;
+                               reg = <0x48304100 0x80>;
+                               ti,hwmods = "ecap2";
+                               status = "disabled";
+                       };
+
+                       ehrpwm2: ehrpwm@48304200 {
+                               compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48304200 0x80>;
+                               ti,hwmods = "ehrpwm2";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss3: epwmss@48306000 {
+                       compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+                       reg = <0x48306000 0x10>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "epwmss3";
+                       status = "disabled";
+
+                       ehrpwm3: ehrpwm@48306200 {
+                               compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48306200 0x80>;
+                               ti,hwmods = "ehrpwm3";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss4: epwmss@48308000 {
+                       compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+                       reg = <0x48308000 0x10>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "epwmss4";
+                       status = "disabled";
+
+                       ehrpwm4: ehrpwm@48308200 {
+                               compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x48308200 0x80>;
+                               ti,hwmods = "ehrpwm4";
+                               status = "disabled";
+                       };
+               };
+
+               epwmss5: epwmss@4830a000 {
+                       compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+                       reg = <0x4830a000 0x10>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "epwmss5";
+                       status = "disabled";
+
+                       ehrpwm5: ehrpwm@4830a200 {
+                               compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                               #pwm-cells = <3>;
+                               reg = <0x4830a200 0x80>;
+                               ti,hwmods = "ehrpwm5";
+                               status = "disabled";
+                       };
+               };
+
+               tscadc: tscadc@44e0d000 {
+                       compatible = "ti,am3359-tscadc";
+                       reg = <0x44e0d000 0x1000>;
+                       ti,hwmods = "adc_tsc";
+                       interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&adc_tsc_fck>;
+                       clock-names = "fck";
+                       status = "disabled";
+
+                       tsc {
+                               compatible = "ti,am3359-tsc";
+                       };
+
+                       adc {
+                               #io-channel-cells = <1>;
+                               compatible = "ti,am3359-adc";
+                       };
+
+               };
+
+               sham: sham@53100000 {
+                       compatible = "ti,omap5-sham";
+                       ti,hwmods = "sham";
+                       reg = <0x53100000 0x300>;
+                       dmas = <&edma 36>;
+                       dma-names = "rx";
+                       interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               aes: aes@53501000 {
+                       compatible = "ti,omap4-aes";
+                       ti,hwmods = "aes";
+                       reg = <0x53501000 0xa0>;
+                       interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&edma 6
+                               &edma 5>;
+                       dma-names = "tx", "rx";
+               };
+
+               des: des@53701000 {
+                       compatible = "ti,omap4-des";
+                       ti,hwmods = "des";
+                       reg = <0x53701000 0xa0>;
+                       interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&edma 34
+                               &edma 33>;
+                       dma-names = "tx", "rx";
+               };
+
+               mcasp0: mcasp@48038000 {
+                       compatible = "ti,am33xx-mcasp-audio";
+                       ti,hwmods = "mcasp0";
+                       reg = <0x48038000 0x2000>,
+                             <0x46000000 0x400000>;
+                       reg-names = "mpu", "dat";
+                       interrupts = <80>, <81>;
+                       interrupt-names = "tx", "rx";
+                       status = "disabled";
+                       dmas = <&edma 8>,
+                              <&edma 9>;
+                       dma-names = "tx", "rx";
+               };
+
+               mcasp1: mcasp@4803C000 {
+                       compatible = "ti,am33xx-mcasp-audio";
+                       ti,hwmods = "mcasp1";
+                       reg = <0x4803C000 0x2000>,
+                             <0x46400000 0x400000>;
+                       reg-names = "mpu", "dat";
+                       interrupts = <82>, <83>;
+                       interrupt-names = "tx", "rx";
+                       status = "disabled";
+                       dmas = <&edma 10>,
+                              <&edma 11>;
+                       dma-names = "tx", "rx";
+               };
+
+               elm: elm@48080000 {
+                       compatible = "ti,am3352-elm";
+                       reg = <0x48080000 0x2000>;
+                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "elm";
+                       clocks = <&l4ls_gclk>;
+                       clock-names = "fck";
+                       status = "disabled";
+               };
+
+               gpmc: gpmc@50000000 {
+                       compatible = "ti,am3352-gpmc";
+                       ti,hwmods = "gpmc";
+                       clocks = <&l3s_gclk>;
+                       clock-names = "fck";
+                       reg = <0x50000000 0x2000>;
+                       interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+                       gpmc,num-cs = <7>;
+                       gpmc,num-waitpins = <2>;
+                       #address-cells = <2>;
+                       #size-cells = <1>;
+                       status = "disabled";
+               };
+
+               am43xx_control_usb2phy1: control-phy@44e10620 {
+                       compatible = "ti,control-phy-usb2-am437";
+                       reg = <0x44e10620 0x4>;
+                       reg-names = "power";
+               };
+
+               am43xx_control_usb2phy2: control-phy@0x44e10628 {
+                       compatible = "ti,control-phy-usb2-am437";
+                       reg = <0x44e10628 0x4>;
+                       reg-names = "power";
+               };
+
+               ocp2scp0: ocp2scp@483a8000 {
+                       compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "ocp2scp0";
+
+                       usb2_phy1: phy@483a8000 {
+                               compatible = "ti,am437x-usb2";
+                               reg = <0x483a8000 0x8000>;
+                               ctrl-module = <&am43xx_control_usb2phy1>;
+                               clocks = <&usb_phy0_always_on_clk32k>,
+                                        <&usb_otg_ss0_refclk960m>;
+                               clock-names = "wkupclk", "refclk";
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+               };
+
+               ocp2scp1: ocp2scp@483e8000 {
+                       compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+                       ti,hwmods = "ocp2scp1";
+
+                       usb2_phy2: phy@483e8000 {
+                               compatible = "ti,am437x-usb2";
+                               reg = <0x483e8000 0x8000>;
+                               ctrl-module = <&am43xx_control_usb2phy2>;
+                               clocks = <&usb_phy1_always_on_clk32k>,
+                                        <&usb_otg_ss1_refclk960m>;
+                               clock-names = "wkupclk", "refclk";
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+               };
+
+               dwc3_1: omap_dwc3@48380000 {
+                       compatible = "ti,am437x-dwc3";
+                       ti,hwmods = "usb_otg_ss0";
+                       reg = <0x48380000 0x10000>;
+                       interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       utmi-mode = <1>;
+                       ranges;
+
+                       usb1: usb@48390000 {
+                               compatible = "synopsys,dwc3";
+                               reg = <0x48390000 0x10000>;
+                               interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&usb2_phy1>;
+                               phy-names = "usb2-phy";
+                               maximum-speed = "high-speed";
+                               dr_mode = "otg";
+                               status = "disabled";
+                               snps,dis_u3_susphy_quirk;
+                               snps,dis_u2_susphy_quirk;
+                       };
+               };
+
+               dwc3_2: omap_dwc3@483c0000 {
+                       compatible = "ti,am437x-dwc3";
+                       ti,hwmods = "usb_otg_ss1";
+                       reg = <0x483c0000 0x10000>;
+                       interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       utmi-mode = <1>;
+                       ranges;
+
+                       usb2: usb@483d0000 {
+                               compatible = "synopsys,dwc3";
+                               reg = <0x483d0000 0x10000>;
+                               interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                               phys = <&usb2_phy2>;
+                               phy-names = "usb2-phy";
+                               maximum-speed = "high-speed";
+                               dr_mode = "otg";
+                               status = "disabled";
+                               snps,dis_u3_susphy_quirk;
+                               snps,dis_u2_susphy_quirk;
+                       };
+               };
+
+               qspi: qspi@47900000 {
+                       compatible = "ti,am4372-qspi";
+                       reg = <0x47900000 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "qspi";
+                       interrupts = <0 138 0x4>;
+                       num-cs = <4>;
+                       status = "disabled";
+               };
+
+               hdq: hdq@48347000 {
+                       compatible = "ti,am4372-hdq";
+                       reg = <0x48347000 0x1000>;
+                       interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&func_12m_clk>;
+                       clock-names = "fck";
+                       ti,hwmods = "hdq1w";
+                       status = "disabled";
+               };
+
+               dss: dss@4832a000 {
+                       compatible = "ti,omap3-dss";
+                       reg = <0x4832a000 0x200>;
+                       status = "disabled";
+                       ti,hwmods = "dss_core";
+                       clocks = <&disp_clk>;
+                       clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       dispc: dispc@4832a400 {
+                               compatible = "ti,omap3-dispc";
+                               reg = <0x4832a400 0x400>;
+                               interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                               ti,hwmods = "dss_dispc";
+                               clocks = <&disp_clk>;
+                               clock-names = "fck";
+                       };
+
+                       rfbi: rfbi@4832a800 {
+                               compatible = "ti,omap3-rfbi";
+                               reg = <0x4832a800 0x100>;
+                               ti,hwmods = "dss_rfbi";
+                               clocks = <&disp_clk>;
+                               clock-names = "fck";
+                               status = "disabled";
+                       };
+               };
+
+               ocmcram: ocmcram@40300000 {
+                       compatible = "mmio-sram";
+                       reg = <0x40300000 0x40000>; /* 256k */
+               };
+
+               dcan0: can@481cc000 {
+                       compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+                       ti,hwmods = "d_can0";
+                       clocks = <&dcan0_fck>;
+                       clock-names = "fck";
+                       reg = <0x481cc000 0x2000>;
+                       syscon-raminit = <&scm_conf 0x644 0>;
+                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               dcan1: can@481d0000 {
+                       compatible = "ti,am4372-d_can", "ti,am3352-d_can";
+                       ti,hwmods = "d_can1";
+                       clocks = <&dcan1_fck>;
+                       clock-names = "fck";
+                       reg = <0x481d0000 0x2000>;
+                       syscon-raminit = <&scm_conf 0x644 1>;
+                       interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               vpfe0: vpfe@48326000 {
+                       compatible = "ti,am437x-vpfe";
+                       reg = <0x48326000 0x2000>;
+                       interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "vpfe0";
+                       status = "disabled";
+               };
+
+               vpfe1: vpfe@48328000 {
+                       compatible = "ti,am437x-vpfe";
+                       reg = <0x48328000 0x2000>;
+                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,hwmods = "vpfe1";
+                       status = "disabled";
+               };
+       };
+};
+
+/include/ "am43xx-clocks.dtsi"
diff --git a/arch/arm/dts/am437x-gp-evm.dts b/arch/arm/dts/am437x-gp-evm.dts
new file mode 100644 (file)
index 0000000..b5f0b4e
--- /dev/null
@@ -0,0 +1,797 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM437x GP EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       model = "TI AM437x GP EVM";
+       compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
+
+       aliases {
+               display0 = &lcd0;
+               serial3 = &uart3;
+       };
+
+       chosen {
+               stdout-path = &uart0;
+       };
+
+       vmmcsd_fixed: fixedregulator-sd {
+               compatible = "regulator-fixed";
+               regulator-name = "vmmcsd_fixed";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               enable-active-high;
+       };
+
+       vtt_fixed: fixedregulator-vtt {
+               compatible = "regulator-fixed";
+               regulator-name = "vtt_fixed";
+               regulator-min-microvolt = <1500000>;
+               regulator-max-microvolt = <1500000>;
+               regulator-always-on;
+               regulator-boot-on;
+               enable-active-high;
+               gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+       };
+
+       vmmcwl_fixed: fixedregulator-mmcwl {
+               compatible = "regulator-fixed";
+               regulator-name = "vmmcwl_fixed";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
+       backlight {
+               compatible = "pwm-backlight";
+               pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+               brightness-levels = <0 51 53 56 62 75 101 152 255>;
+               default-brightness-level = <8>;
+       };
+
+       matrix_keypad: matrix_keypad@0 {
+               compatible = "gpio-matrix-keypad";
+               debounce-delay-ms = <5>;
+               col-scan-delay-us = <2>;
+
+               row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
+                               &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
+                               &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
+
+               col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
+                               &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
+
+               linux,keymap = <0x00000201      /* P1 */
+                               0x00010202      /* P2 */
+                               0x01000067      /* UP */
+                               0x0101006a      /* RIGHT */
+                               0x02000069      /* LEFT */
+                               0x0201006c>;      /* DOWN */
+               };
+
+       lcd0: display {
+               compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+               label = "lcd";
+
+               pinctrl-names = "default";
+               pinctrl-0 = <&lcd_pins>;
+
+               /*
+                * SelLCDorHDMI, LOW to select HDMI. This is not really the
+                * panel's enable GPIO, but we don't have HDMI driver support nor
+                * support to switch between two displays, so using this gpio as
+                * panel's enable should be safe.
+                */
+               enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+
+               panel-timing {
+                       clock-frequency = <33000000>;
+                       hactive = <800>;
+                       vactive = <480>;
+                       hfront-porch = <210>;
+                       hback-porch = <16>;
+                       hsync-len = <30>;
+                       vback-porch = <10>;
+                       vfront-porch = <22>;
+                       vsync-len = <13>;
+                       hsync-active = <0>;
+                       vsync-active = <0>;
+                       de-active = <1>;
+                       pixelclk-active = <1>;
+               };
+
+               port {
+                       lcd_in: endpoint {
+                               remote-endpoint = <&dpi_out>;
+                       };
+               };
+       };
+
+       /* fixed 12MHz oscillator */
+       refclk: oscillator {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <12000000>;
+       };
+
+};
+
+&am43xx_pinmux {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&wlan_pins_default>;
+       pinctrl-1 = <&wlan_pins_sleep>;
+
+       i2c0_pins: i2c0_pins {
+               pinctrl-single,pins = <
+                       0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
+                       0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
+               >;
+       };
+
+       i2c1_pins: i2c1_pins {
+               pinctrl-single,pins = <
+                       0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
+                       0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
+               >;
+       };
+
+       mmc1_pins: pinmux_mmc1_pins {
+               pinctrl-single,pins = <
+                       0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+               >;
+       };
+
+       ecap0_pins: backlight_pins {
+               pinctrl-single,pins = <
+                       0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+               >;
+       };
+
+       pixcir_ts_pins: pixcir_ts_pins {
+               pinctrl-single,pins = <
+                       0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
+               >;
+       };
+
+       cpsw_default: cpsw_default {
+               pinctrl-single,pins = <
+                       /* Slave 1 */
+                       0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
+                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
+                       0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
+                       0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
+                       0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
+                       0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
+                       0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
+                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
+                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
+                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
+                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
+                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
+               >;
+       };
+
+       cpsw_sleep: cpsw_sleep {
+               pinctrl-single,pins = <
+                       /* Slave 1 reset value */
+                       0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+               >;
+       };
+
+       davinci_mdio_default: davinci_mdio_default {
+               pinctrl-single,pins = <
+                       /* MDIO */
+                       0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                       0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+               >;
+       };
+
+       davinci_mdio_sleep: davinci_mdio_sleep {
+               pinctrl-single,pins = <
+                       /* MDIO reset value */
+                       0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+               >;
+       };
+
+       nand_flash_x8: nand_flash_x8 {
+               pinctrl-single,pins = <
+                       0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* spi2_cs0.gpio/eMMCorNANDsel */
+                       0x0  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
+                       0x4  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
+                       0x8  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
+                       0xc  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
+                       0x10 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
+                       0x14 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
+                       0x18 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
+                       0x1c (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
+                       0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                       0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
+                       0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
+                       0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
+                       0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
+                       0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
+                       0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+               >;
+       };
+
+       dss_pins: dss_pins {
+               pinctrl-single,pins = <
+                       0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+                       0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
+                       0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+                       0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+                       0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
+                       0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+                       0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+                       0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+                       0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+                       0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+
+               >;
+       };
+
+       lcd_pins: lcd_pins {
+               pinctrl-single,pins = <
+                       /* GPIO 5_8 to select LCD / HDMI */
+                       0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
+               >;
+       };
+
+       dcan0_default: dcan0_default_pins {
+               pinctrl-single,pins = <
+                       0x178 (PIN_OUTPUT | MUX_MODE2)          /* uart1_ctsn.d_can0_tx */
+                       0x17c (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_rtsn.d_can0_rx */
+               >;
+       };
+
+       dcan1_default: dcan1_default_pins {
+               pinctrl-single,pins = <
+                       0x180 (PIN_OUTPUT | MUX_MODE2)          /* uart1_rxd.d_can1_tx */
+                       0x184 (PIN_INPUT_PULLUP | MUX_MODE2)    /* uart1_txd.d_can1_rx */
+               >;
+       };
+
+       vpfe0_pins_default: vpfe0_pins_default {
+               pinctrl-single,pins = <
+                       0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
+                       0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
+                       0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
+                       0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
+                       0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
+                       0x208 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
+                       0x20C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
+                       0x210 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
+                       0x214 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
+                       0x218 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
+                       0x21C (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
+                       0x220 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
+                       0x224 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
+               >;
+       };
+
+       vpfe0_pins_sleep: vpfe0_pins_sleep {
+               pinctrl-single,pins = <
+                       0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
+                       0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
+                       0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
+                       0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
+                       0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
+                       0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
+                       0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
+                       0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
+                       0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
+                       0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
+                       0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
+                       0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
+                       0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
+               >;
+       };
+
+       vpfe1_pins_default: vpfe1_pins_default {
+               pinctrl-single,pins = <
+                       0x1CC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
+                       0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
+                       0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
+                       0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
+                       0x1DC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
+                       0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
+                       0x1EC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
+                       0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
+                       0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
+                       0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
+                       0x1FC (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
+                       0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
+                       0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
+               >;
+       };
+
+       vpfe1_pins_sleep: vpfe1_pins_sleep {
+               pinctrl-single,pins = <
+                       0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
+                       0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
+                       0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
+                       0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
+                       0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
+                       0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
+                       0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
+                       0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
+                       0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
+                       0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
+                       0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
+                       0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
+                       0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
+               >;
+       };
+
+       mmc3_pins_default: pinmux_mmc3_pins_default {
+               pinctrl-single,pins = <
+                       0x8c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
+                       0x88 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
+                       0x44 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
+                       0x48 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
+                       0x4c (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
+                       0x78 (PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
+               >;
+       };
+
+       mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
+               pinctrl-single,pins = <
+                       0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_clk.mmc2_clk */
+                       0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_csn3.mmc2_cmd */
+                       0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a1.mmc2_dat0 */
+                       0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a2.mmc2_dat1 */
+                       0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a3.mmc2_dat2 */
+                       0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_be1n.mmc2_dat3 */
+               >;
+       };
+
+       wlan_pins_default: pinmux_wlan_pins_default {
+               pinctrl-single,pins = <
+                       0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
+                       0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
+                       0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a0.gpio1_16 BT_EN*/
+               >;
+       };
+
+       wlan_pins_sleep: pinmux_wlan_pins_sleep {
+               pinctrl-single,pins = <
+                       0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)          /* gpmc_a4.gpio1_20 WL_EN */
+                       0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)    /* gpmc_a7.gpio1_23 WL_IRQ*/
+                       0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
+               >;
+       };
+
+       uart3_pins: uart3_pins {
+               pinctrl-single,pins = <
+                       0x228 (PIN_INPUT | MUX_MODE0)           /* uart3_rxd.uart3_rxd */
+                       0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
+                       0x230 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_ctsn.uart3_ctsn */
+                       0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
+               >;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+       clock-frequency = <100000>;
+
+       tps65218: tps65218@24 {
+               reg = <0x24>;
+               compatible = "ti,tps65218";
+               interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+               interrupt-controller;
+               #interrupt-cells = <2>;
+
+               dcdc1: regulator-dcdc1 {
+                       compatible = "ti,tps65218-dcdc1";
+                       regulator-name = "vdd_core";
+                       regulator-min-microvolt = <912000>;
+                       regulator-max-microvolt = <1144000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               dcdc2: regulator-dcdc2 {
+                       compatible = "ti,tps65218-dcdc2";
+                       regulator-name = "vdd_mpu";
+                       regulator-min-microvolt = <912000>;
+                       regulator-max-microvolt = <1378000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+
+               dcdc3: regulator-dcdc3 {
+                       compatible = "ti,tps65218-dcdc3";
+                       regulator-name = "vdcdc3";
+                       regulator-min-microvolt = <1500000>;
+                       regulator-max-microvolt = <1500000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+               dcdc5: regulator-dcdc5 {
+                       compatible = "ti,tps65218-dcdc5";
+                       regulator-name = "v1_0bat";
+                       regulator-min-microvolt = <1000000>;
+                       regulator-max-microvolt = <1000000>;
+               };
+
+               dcdc6: regulator-dcdc6 {
+                       compatible = "ti,tps65218-dcdc6";
+                       regulator-name = "v1_8bat";
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+               };
+
+               ldo1: regulator-ldo1 {
+                       compatible = "ti,tps65218-ldo1";
+                       regulator-min-microvolt = <1800000>;
+                       regulator-max-microvolt = <1800000>;
+                       regulator-boot-on;
+                       regulator-always-on;
+               };
+       };
+
+       ov2659@30 {
+               compatible = "ovti,ov2659";
+               reg = <0x30>;
+
+               clocks = <&refclk 0>;
+               clock-names = "xvclk";
+
+               port {
+                       ov2659_0: endpoint {
+                               remote-endpoint = <&vpfe1_ep>;
+                               link-frequencies = /bits/ 64 <70000000>;
+                       };
+               };
+       };
+};
+
+&i2c1 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c1_pins>;
+       pixcir_ts@5c {
+               compatible = "pixcir,pixcir_tangoc";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pixcir_ts_pins>;
+               reg = <0x5c>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <22 0>;
+
+               attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+
+               touchscreen-size-x = <1024>;
+               touchscreen-size-y = <600>;
+       };
+
+       ov2659@30 {
+               compatible = "ovti,ov2659";
+               reg = <0x30>;
+
+               clocks = <&refclk 0>;
+               clock-names = "xvclk";
+
+               port {
+                       ov2659_1: endpoint {
+                               remote-endpoint = <&vpfe0_ep>;
+                               link-frequencies = /bits/ 64 <70000000>;
+                       };
+               };
+       };
+};
+
+&epwmss0 {
+       status = "okay";
+};
+
+&tscadc {
+       status = "okay";
+
+       adc {
+               ti,adc-channels = <0 1 2 3 4 5 6 7>;
+       };
+};
+
+&ecap0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&ecap0_pins>;
+};
+
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio3 {
+       status = "okay";
+};
+
+&gpio4 {
+       status = "okay";
+};
+
+&gpio5 {
+       status = "okay";
+       ti,no-reset-on-init;
+};
+
+&mmc1 {
+       status = "okay";
+       vmmc-supply = <&vmmcsd_fixed>;
+       bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pins>;
+       cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+};
+
+&mmc3 {
+       /* disable MMC3 as SDIO is not supported in U-Boot */
+       status = "disabled";
+       /* these are on the crossbar and are outlined in the
+          xbar-event-map element */
+       dmas = <&edma 30
+               &edma 31>;
+       dma-names = "tx", "rx";
+       vmmc-supply = <&vmmcwl_fixed>;
+       bus-width = <4>;
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&mmc3_pins_default>;
+       pinctrl-1 = <&mmc3_pins_sleep>;
+       cap-power-off-card;
+       keep-power-in-suspend;
+       ti,non-removable;
+
+       #address-cells = <1>;
+       #size-cells = <0>;
+       wlcore: wlcore@0 {
+               compatible = "ti,wl1835";
+               reg = <2>;
+               interrupt-parent = <&gpio1>;
+               interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+       };
+};
+
+&edma {
+       ti,edma-xbar-event-map = /bits/ 16 <1 30
+                                           2 31>;
+};
+
+&uart3 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart3_pins>;
+};
+
+&usb2_phy1 {
+       status = "okay";
+};
+
+&usb1 {
+       dr_mode = "peripheral";
+       status = "okay";
+};
+
+&usb2_phy2 {
+       status = "okay";
+};
+
+&usb2 {
+       dr_mode = "host";
+       status = "okay";
+};
+
+&mac {
+       slaves = <1>;
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&cpsw_default>;
+       pinctrl-1 = <&cpsw_sleep>;
+       status = "okay";
+};
+
+&davinci_mdio {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&davinci_mdio_default>;
+       pinctrl-1 = <&davinci_mdio_sleep>;
+       status = "okay";
+};
+
+&cpsw_emac0 {
+       phy_id = <&davinci_mdio>, <0>;
+       phy-mode = "rgmii";
+};
+
+&elm {
+       status = "okay";
+};
+
+&gpmc {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&nand_flash_x8>;
+       ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+       nand@0,0 {
+               reg = <0 0 4>;          /* device IO registers */
+               ti,nand-ecc-opt = "bch16";
+               ti,elm-id = <&elm>;
+               nand-bus-width = <8>;
+               gpmc,device-width = <1>;
+               gpmc,sync-clk-ps = <0>;
+               gpmc,cs-on-ns = <0>;
+               gpmc,cs-rd-off-ns = <40>;
+               gpmc,cs-wr-off-ns = <40>;
+               gpmc,adv-on-ns = <0>;
+               gpmc,adv-rd-off-ns = <25>;
+               gpmc,adv-wr-off-ns = <25>;
+               gpmc,we-on-ns = <0>;
+               gpmc,we-off-ns = <20>;
+               gpmc,oe-on-ns = <3>;
+               gpmc,oe-off-ns = <30>;
+               gpmc,access-ns = <30>;
+               gpmc,rd-cycle-ns = <40>;
+               gpmc,wr-cycle-ns = <40>;
+               gpmc,wait-pin = <0>;
+               gpmc,bus-turnaround-ns = <0>;
+               gpmc,cycle2cycle-delay-ns = <0>;
+               gpmc,clk-activation-ns = <0>;
+               gpmc,wait-monitoring-ns = <0>;
+               gpmc,wr-access-ns = <40>;
+               gpmc,wr-data-mux-bus-ns = <0>;
+               /* MTD partition table */
+               /* All SPL-* partitions are sized to minimal length
+                * which can be independently programmable. For
+                * NAND flash this is equal to size of erase-block */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               partition@0 {
+                       label = "NAND.SPL";
+                       reg = <0x00000000 0x00040000>;
+               };
+               partition@1 {
+                       label = "NAND.SPL.backup1";
+                       reg = <0x00040000 0x00040000>;
+               };
+               partition@2 {
+                       label = "NAND.SPL.backup2";
+                       reg = <0x00080000 0x00040000>;
+               };
+               partition@3 {
+                       label = "NAND.SPL.backup3";
+                       reg = <0x000c0000 0x00040000>;
+               };
+               partition@4 {
+                       label = "NAND.u-boot-spl-os";
+                       reg = <0x00100000 0x00080000>;
+               };
+               partition@5 {
+                       label = "NAND.u-boot";
+                       reg = <0x00180000 0x00100000>;
+               };
+               partition@6 {
+                       label = "NAND.u-boot-env";
+                       reg = <0x00280000 0x00040000>;
+               };
+               partition@7 {
+                       label = "NAND.u-boot-env.backup1";
+                       reg = <0x002c0000 0x00040000>;
+               };
+               partition@8 {
+                       label = "NAND.kernel";
+                       reg = <0x00300000 0x00700000>;
+               };
+               partition@9 {
+                       label = "NAND.file-system";
+                       reg = <0x00a00000 0x1f600000>;
+               };
+       };
+};
+
+&dss {
+       status = "ok";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&dss_pins>;
+
+       port {
+               dpi_out: endpoint@0 {
+                       remote-endpoint = <&lcd_in>;
+                       data-lines = <24>;
+               };
+       };
+};
+
+&dcan0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&dcan0_default>;
+       status = "okay";
+};
+
+&dcan1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&dcan1_default>;
+       status = "okay";
+};
+
+&vpfe0 {
+       status = "okay";
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&vpfe0_pins_default>;
+       pinctrl-1 = <&vpfe0_pins_sleep>;
+
+       port {
+               vpfe0_ep: endpoint {
+                       remote-endpoint = <&ov2659_1>;
+                       ti,am437x-vpfe-interface = <0>;
+                       bus-width = <8>;
+                       hsync-active = <0>;
+                       vsync-active = <0>;
+               };
+       };
+};
+
+&vpfe1 {
+       status = "okay";
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&vpfe1_pins_default>;
+       pinctrl-1 = <&vpfe1_pins_sleep>;
+
+       port {
+               vpfe1_ep: endpoint {
+                       remote-endpoint = <&ov2659_0>;
+                       ti,am437x-vpfe-interface = <0>;
+                       bus-width = <8>;
+                       hsync-active = <0>;
+                       vsync-active = <0>;
+               };
+       };
+};
diff --git a/arch/arm/dts/am43xx-clocks.dtsi b/arch/arm/dts/am43xx-clocks.dtsi
new file mode 100644 (file)
index 0000000..d0c0dfa
--- /dev/null
@@ -0,0 +1,757 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scm_clocks {
+       sys_clkin_ck: sys_clkin_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
+               ti,bit-shift = <31>;
+               reg = <0x0040>;
+       };
+
+       crystal_freq_sel_ck: crystal_freq_sel_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+               ti,bit-shift = <29>;
+               reg = <0x0040>;
+       };
+
+       sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+               ti,bit-shift = <22>;
+               reg = <0x0040>;
+       };
+
+       adc_tsc_fck: adc_tsc_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       dcan0_fck: dcan0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       dcan1_fck: dcan1_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       mcasp0_fck: mcasp0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       mcasp1_fck: mcasp1_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       smartreflex0_fck: smartreflex0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       smartreflex1_fck: smartreflex1_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       sha0_fck: sha0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       aes0_fck: aes0_fck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       ehrpwm0_tbclk: ehrpwm0_tbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <0>;
+               reg = <0x0664>;
+       };
+
+       ehrpwm1_tbclk: ehrpwm1_tbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <1>;
+               reg = <0x0664>;
+       };
+
+       ehrpwm2_tbclk: ehrpwm2_tbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <2>;
+               reg = <0x0664>;
+       };
+
+       ehrpwm3_tbclk: ehrpwm3_tbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <4>;
+               reg = <0x0664>;
+       };
+
+       ehrpwm4_tbclk: ehrpwm4_tbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <5>;
+               reg = <0x0664>;
+       };
+
+       ehrpwm5_tbclk: ehrpwm5_tbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&l4ls_gclk>;
+               ti,bit-shift = <6>;
+               reg = <0x0664>;
+       };
+};
+&prcm_clocks {
+       clk_32768_ck: clk_32768_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+       };
+
+       clk_rc32k_ck: clk_rc32k_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+       };
+
+       virt_19200000_ck: virt_19200000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <19200000>;
+       };
+
+       virt_24000000_ck: virt_24000000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+       };
+
+       virt_25000000_ck: virt_25000000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <25000000>;
+       };
+
+       virt_26000000_ck: virt_26000000_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <26000000>;
+       };
+
+       tclkin_ck: tclkin_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <26000000>;
+       };
+
+       dpll_core_ck: dpll_core_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-core-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+       };
+
+       dpll_core_x2_ck: dpll_core_x2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-x2-clock";
+               clocks = <&dpll_core_ck>;
+       };
+
+       dpll_core_m4_ck: dpll_core_m4_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_core_x2_ck>;
+               ti,max-div = <31>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2d38>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       dpll_core_m5_ck: dpll_core_m5_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_core_x2_ck>;
+               ti,max-div = <31>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2d3c>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       dpll_core_m6_ck: dpll_core_m6_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_core_x2_ck>;
+               ti,max-div = <31>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2d40>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       dpll_mpu_ck: dpll_mpu_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+       };
+
+       dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_mpu_ck>;
+               ti,max-div = <31>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2d70>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       dpll_ddr_ck: dpll_ddr_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x2da0>, <0x2da4>, <0x2dac>;
+       };
+
+       dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_ddr_ck>;
+               ti,max-div = <31>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2db0>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       dpll_disp_ck: dpll_disp_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+       };
+
+       dpll_disp_m2_ck: dpll_disp_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_disp_ck>;
+               ti,max-div = <31>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2e30>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+               ti,set-rate-parent;
+       };
+
+       dpll_per_ck: dpll_per_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-j-type-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x2de0>, <0x2de4>, <0x2dec>;
+       };
+
+       dpll_per_m2_ck: dpll_per_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_per_ck>;
+               ti,max-div = <127>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2df0>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <4>;
+       };
+
+       dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <4>;
+       };
+
+       clk_24mhz: clk_24mhz {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <8>;
+       };
+
+       clkdiv32k_ck: clkdiv32k_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&clk_24mhz>;
+               clock-mult = <1>;
+               clock-div = <732>;
+       };
+
+       clkdiv32k_ick: clkdiv32k_ick {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ck>;
+               ti,bit-shift = <8>;
+               reg = <0x2a38>;
+       };
+
+       sysclk_div: sysclk_div {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       pruss_ocp_gclk: pruss_ocp_gclk {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+               reg = <0x4248>;
+       };
+
+       clk_32k_tpm_ck: clk_32k_tpm_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+       };
+
+       timer1_fck: timer1_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+               reg = <0x4200>;
+       };
+
+       timer2_fck: timer2_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x4204>;
+       };
+
+       timer3_fck: timer3_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x4208>;
+       };
+
+       timer4_fck: timer4_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x420c>;
+       };
+
+       timer5_fck: timer5_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x4210>;
+       };
+
+       timer6_fck: timer6_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x4214>;
+       };
+
+       timer7_fck: timer7_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+               reg = <0x4218>;
+       };
+
+       wdt1_fck: wdt1_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+               reg = <0x422c>;
+       };
+
+       l3_gclk: l3_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sysclk_div>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       l4hs_gclk: l4hs_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       l3s_gclk: l3s_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_div2_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       l4ls_gclk: l4ls_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m4_div2_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m5_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+               reg = <0x4238>;
+       };
+
+       clk_32k_mosc_ck: clk_32k_mosc_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+       };
+
+       gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+               reg = <0x4240>;
+       };
+
+       gpio0_dbclk: gpio0_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&gpio0_dbclk_mux_ck>;
+               ti,bit-shift = <8>;
+               reg = <0x2b68>;
+       };
+
+       gpio1_dbclk: gpio1_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <8>;
+               reg = <0x8c78>;
+       };
+
+       gpio2_dbclk: gpio2_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <8>;
+               reg = <0x8c80>;
+       };
+
+       gpio3_dbclk: gpio3_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <8>;
+               reg = <0x8c88>;
+       };
+
+       gpio4_dbclk: gpio4_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <8>;
+               reg = <0x8c90>;
+       };
+
+       gpio5_dbclk: gpio5_dbclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&clkdiv32k_ick>;
+               ti,bit-shift = <8>;
+               reg = <0x8c98>;
+       };
+
+       mmc_clk: mmc_clk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+               ti,bit-shift = <1>;
+               reg = <0x423c>;
+       };
+
+       gfx_fck_div_ck: gfx_fck_div_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&gfx_fclk_clksel_ck>;
+               reg = <0x423c>;
+               ti,max-div = <2>;
+       };
+
+       disp_clk: disp_clk {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+               reg = <0x4244>;
+               ti,set-rate-parent;
+       };
+
+       dpll_extdev_ck: dpll_extdev_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+       };
+
+       dpll_extdev_m2_ck: dpll_extdev_m2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_extdev_ck>;
+               ti,max-div = <127>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2e70>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       mux_synctimer32k_ck: mux_synctimer32k_ck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+               reg = <0x4230>;
+       };
+
+       synctimer_32kclk: synctimer_32kclk {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&mux_synctimer32k_ck>;
+               ti,bit-shift = <8>;
+               reg = <0x2a30>;
+       };
+
+       timer8_fck: timer8_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+               reg = <0x421c>;
+       };
+
+       timer9_fck: timer9_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+               reg = <0x4220>;
+       };
+
+       timer10_fck: timer10_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+               reg = <0x4224>;
+       };
+
+       timer11_fck: timer11_fck {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+               reg = <0x4228>;
+       };
+
+       cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_core_m5_ck>;
+               clock-mult = <1>;
+               clock-div = <1>;
+       };
+
+       cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&cpsw_50m_clkdiv>;
+               clock-mult = <1>;
+               clock-div = <10>;
+       };
+
+       dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-x2-clock";
+               clocks = <&dpll_ddr_ck>;
+       };
+
+       dpll_ddr_m4_ck: dpll_ddr_m4_ck {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&dpll_ddr_x2_ck>;
+               ti,max-div = <31>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2db8>;
+               ti,index-starts-at-one;
+               ti,invert-autoidle-bit;
+       };
+
+       dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+               #clock-cells = <0>;
+               compatible = "ti,fixed-factor-clock";
+               clocks = <&dpll_per_ck>;
+               ti,clock-mult = <1>;
+               ti,clock-div = <1>;
+               ti,autoidle-shift = <8>;
+               reg = <0x2e14>;
+               ti,invert-autoidle-bit;
+       };
+
+       dll_aging_clk_div: dll_aging_clk_div {
+               #clock-cells = <0>;
+               compatible = "ti,divider-clock";
+               clocks = <&sys_clkin_ck>;
+               reg = <0x4250>;
+               ti,dividers = <8>, <16>, <32>;
+       };
+
+       div_core_25m_ck: div_core_25m_ck {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sysclk_div>;
+               clock-mult = <1>;
+               clock-div = <8>;
+       };
+
+       func_12m_clk: func_12m_clk {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&dpll_per_m2_ck>;
+               clock-mult = <1>;
+               clock-div = <16>;
+       };
+
+       vtp_clk_div: vtp_clk_div {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clocks = <&sys_clkin_ck>;
+               clock-mult = <1>;
+               clock-div = <2>;
+       };
+
+       usbphy_32khz_clkmux: usbphy_32khz_clkmux {
+               #clock-cells = <0>;
+               compatible = "ti,mux-clock";
+               clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+               reg = <0x4260>;
+       };
+
+       usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&usbphy_32khz_clkmux>;
+               ti,bit-shift = <8>;
+               reg = <0x2a40>;
+       };
+
+       usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&usbphy_32khz_clkmux>;
+               ti,bit-shift = <8>;
+               reg = <0x2a48>;
+       };
+
+       usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&dpll_per_clkdcoldo>;
+               ti,bit-shift = <8>;
+               reg = <0x8a60>;
+       };
+
+       usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+               #clock-cells = <0>;
+               compatible = "ti,gate-clock";
+               clocks = <&dpll_per_clkdcoldo>;
+               ti,bit-shift = <8>;
+               reg = <0x8a68>;
+       };
+};
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig
new file mode 100644 (file)
index 0000000..53fb0bf
--- /dev/null
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_DISABLE_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_MMC=y
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
new file mode 100644 (file)
index 0000000..7203687
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * This header provides constants specific to AM43XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H
+#define _DT_BINDINGS_PINCTRL_AM43XX_H
+
+#define MUX_MODE0      0
+#define MUX_MODE1      1
+#define MUX_MODE2      2
+#define MUX_MODE3      3
+#define MUX_MODE4      4
+#define MUX_MODE5      5
+#define MUX_MODE6      6
+#define MUX_MODE7      7
+#define MUX_MODE8      8
+
+#define PULL_DISABLE           (1 << 16)
+#define PULL_UP                        (1 << 17)
+#define INPUT_EN               (1 << 18)
+#define SLEWCTRL_SLOW          (1 << 19)
+#define SLEWCTRL_FAST          0
+#define DS0_PULL_UP_DOWN_EN    (1 << 27)
+#define WAKEUP_ENABLE          (1 << 29)
+
+#define PIN_OUTPUT             (PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP      (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN    0
+#define PIN_INPUT              (INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP       (INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN     (INPUT_EN)
+
+#endif
diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h
new file mode 100644 (file)
index 0000000..96f49e8
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * This header provides constants for most PWM bindings.
+ *
+ * Most PWM bindings can include a flags cell as part of the PWM specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_PWM_PWM_H
+#define _DT_BINDINGS_PWM_PWM_H
+
+#define PWM_POLARITY_INVERTED                  (1 << 0)
+
+#endif