+#if (defined (__sparc_v9__) || (defined (__sparc__) && defined (__arch64__)) \
+ || defined (__sparcv9)) && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+ __asm__ ("addcc %4,%5,%1
+ add %2,%3,%0
+ bcs,a,pn %%xcc, 1f
+ add %0, 1, %0
+ 1:" \
+ : "=r" ((UDItype)(sh)), \
+ "=&r" ((UDItype)(sl)) \
+ : "r" ((UDItype)(ah)), \
+ "r" ((UDItype)(bh)), \
+ "r" ((UDItype)(al)), \
+ "r" ((UDItype)(bl)) \
+ : "cc")
+
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+ __asm__ ("subcc %4,%5,%1
+ sub %2,%3,%0
+ bcs,a,pn %%xcc, 1f
+ sub %0, 1, %0
+ 1:" \
+ : "=r" ((UDItype)(sh)), \
+ "=&r" ((UDItype)(sl)) \
+ : "r" ((UDItype)(ah)), \
+ "r" ((UDItype)(bh)), \
+ "r" ((UDItype)(al)), \
+ "r" ((UDItype)(bl)) \
+ : "cc")
+
+#define umul_ppmm(wh, wl, u, v) \
+ do { \
+ UDItype tmp1, tmp2, tmp3, tmp4; \
+ __asm__ __volatile__ ( \
+ "srl %7,0,%3
+ mulx %3,%6,%1
+ srlx %6,32,%2
+ mulx %2,%3,%4
+ sllx %4,32,%5
+ srl %6,0,%3
+ sub %1,%5,%5
+ srlx %5,32,%5
+ addcc %4,%5,%4
+ srlx %7,32,%5
+ mulx %3,%5,%3
+ mulx %2,%5,%5
+ sethi 0x80000000,%2
+ addcc %4,%3,%4
+ srlx %4,32,%4
+ add %2,%2,%2
+ movcc %%xcc,%%g0,%2
+ addcc %5,%4,%5
+ sllx %3,32,%3
+ add %1,%3,%1
+ add %5,%2,%0" \
+ : "=r" ((UDItype)(wh)), \
+ "=&r" ((UDItype)(wl)), \
+ "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
+ : "r" ((UDItype)(u)), \
+ "r" ((UDItype)(v)) \
+ : "cc"); \
+ } while (0)
+#define UMUL_TIME 96
+#endif /* __sparc_v9__ */
+