+commit 218ca724c08ca8a649f0917cf201cf23d4b33f39
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Mar 26 10:40:12 2008 +0100
+
+ README: update documentation (availability, links, etc.)
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f6b44e0e4d18fe507833a0f76d24a9aa72c123f1
+Author: Aras Vaichas <arasv@magtech.com.au>
+Date: Tue Mar 25 12:09:07 2008 +1100
+
+ USB Storage, add meaningful return value
+
+ This patch changes the "usb storage" command to return success if it
+ finds a USB storage device, otherwise it returns error.
+
+ Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 18e69a35efbb078403db0c0063986470dad7d082
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Fri Mar 14 23:20:18 2008 +0300
+
+ 83xx/fdt_support: let user specifiy FSL USB Dual-Role controller role
+
+ Linux understands "host" (default), "peripheral" and "otg" (broken).
+ Though, U-Boot doesn't restrict dr_mode variable to these values (think
+ of renames in future).
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit c7604783b236e368f225efb7b3efb418fe20b404
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Fri Mar 14 23:20:30 2008 +0300
+
+ tsec: fix link detection for the RTL8211B PHY
+
+ RTL8211B sets link state register after autonegotiation complete,
+ so with bootdelay=0 RTL8211B will report lack of the link.
+
+ To fix this, we should wait for aneg to complete, even if the
+ link is currently down.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 7fa9cbb00dc83fcf175042b6f20c2c9bce9a15f4
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:47:09 2008 +0300
+
+ mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixups
+
+ device_type = "soc" is being deprecated, newer device trees will use
+ "fsl,soc" and/or "fsl,immr" for the soc nodes.
+
+ This patch also adds clock-frequency property for soc nodes (the same
+ value as bus-frequency).
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07
+Author: Joe D'Abbraccio <ljd015@freescale.com>
+Date: Mon Mar 24 13:00:59 2008 -0400
+
+ Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock
+
+ With the original value of 1/2 clock cycle delay, the system ran relatively
+ stable except when we run benchmarks that are intensive users of memory.
+ When I run samba connected disk with a HDBENCH test, the system locks-up
+ or reboots sporadically.
+
+ Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
+
+commit a7ba32d480a86db5db8dcd8ca66b21b4cadda923
+Author: Scott Wood <scottwood@freescale.com>
+Date: Mon Mar 24 12:44:13 2008 -0500
+
+ mpc83xx: Set PCI I/O bus-address base to zero.
+
+ The device trees for these boards describe PCI I/O as starting from
+ address zero from the device's perspective.
+
+ Placing I/O elsewhere may cause problems with certain PCI boards, and may
+ cause problems with Linux.
+
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
+commit f700e7df7fecf2d3765ae568ce77ce788cde4f3e
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:47:05 2008 +0300
+
+ mpc83xx: MPC8360E-RDK: use 33.3(3)MHz CLKIN/SYS_CLK
+
+ At least on the "33MHz Pilot" board crystal is actually 33.3MHz.
+ This patch fixes "system time drifting" problem.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 3a0cfdd576dc9b16d1468d37339182607c697fb7
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:47:02 2008 +0300
+
+ mpc83xx: MPC8360E-RDK: define CONFIG_OF_STDOUT_VIA_ALIAS
+
+ This is needed to update /choosen/linux,stdout-path properly.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 3419eb62f088d7a22f1d2a3cebf76b77e408b5b9
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:47:00 2008 +0300
+
+ mpc83xx: MPC8360E-RDK: add dhcp command
+
+ Plus modify environment to use it and remove bootfile env variable,
+ it is internal and CONFIG_BOOTFILE is used for these purposes.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit d892b2dbb4087a26778bfd42470c3ea7d0e2b6aa
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:46:57 2008 +0300
+
+ mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc
+
+ Current DDR setup easily causes memory corruption, this patch fixes it.
+
+ Also fix TIMING_CFG0_MRS_CYC definition.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit d47d49cc37a38f2719a3e1b9bbe08ac810cf2d9a
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:46:53 2008 +0300
+
+ mpc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCI
+
+ This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen
+ controller and FHCI (QE USB).
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 7ad959490962e6842648d87d4bd795ea6cdcce67
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:46:51 2008 +0300
+
+ mpc83xx: MPC8360E-RDK: add support for NAND
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 9a3e832aeb491861d029991241572ebdf4b5b61b
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:46:46 2008 +0300
+
+ mpc83xx: MPC8360E-RDK: use RGMII_RXID interface mode
+
+ This is needed for BCM PHYs to work on this board.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 300615dc5d9b0a2022fbc6af0c13159e33fd752e
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:46:34 2008 +0300
+
+ uec: add support for Broadcom BCM5481 Gigabit PHY
+
+ This patch adds basic support for Broadcom BCM5481 PHY.
+
+ RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is
+ Peter Barada <peterb@logicpd.com>.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 6a600c3a1876bc203445df4f0fd6b12648259666
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:46:28 2008 +0300
+
+ uec: add support for RGMII_RXID interface mode
+
+ PHY drivers will use it to setup software delay between RXD and RXC
+ signals.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 91cdaa3a9d7562b869d96774e9c9ddf142c0848d
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 20:46:24 2008 +0300
+
+ uec: add support for gbit mii status readings
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit aabce7fb505ffe55ebf3bf4dcafdae97a581558d
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 17:40:47 2008 +0300
+
+ 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boards
+
+ This is primarily for the early console support.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 2bd7460e9283ec98565189b3cdbcfb2bcdcdd635
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 17:40:43 2008 +0300
+
+ 83xx: initialize serdes for MPC837XRDB boards
+
+ On the MPC8377ERDB: 2 SATA and 2 PCI-E.
+ On the MPC8378ERDB: 2 PCI-E
+ On the MPC8379ERDB: 4 SATA
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 453316a2a19642d8afcbca7452e40a6b44a197b1
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 17:40:32 2008 +0300
+
+ 83xx: serdes setup routines
+
+ This patch adds few routines to configure serdes on 837x targets.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit a796cdf9c377cb4e5d61d1079a296608f8fbd903
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 17:40:27 2008 +0300
+
+ 83xx: split COBJS onto separate lines
+
+ ..plus get rid of some #ifdefs in the .c files.
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 46a3aeea73c13ab04ebf7a8739afb87ac5da94a3
+Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+Date: Mon Mar 24 17:40:23 2008 +0300
+
+ 83xx: nand support for MPC837XRDB boards
+
+ Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
+
+commit 82e45a204190593e8613145a928f998fb8c909c4
+Author: Jerry Van Baren <gvb.uboot@gmail.com>
+Date: Tue Mar 18 21:44:41 2008 -0400
+
+ Enable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS.
+
+ Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 0fa7a1b4719e325fce332689fb8754ec166191ff
+Author: Michael Barkowski <michael.barkowski@freescale.com>
+Date: Thu Mar 20 13:15:39 2008 -0400
+
+ mpc8323erdb: remove RTC and add EEPROM
+
+ There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM.
+
+ Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 5bbeea86eb6afb872374cd23217cb3c1018443ed
+Author: Michael Barkowski <michael.barkowski@freescale.com>
+Date: Thu Mar 20 13:15:34 2008 -0400
+
+ mpc8323erdb: Improve the system performance
+
+ The following changes are based on kernel UCC ethernet performance:
+
+ 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
+ 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
+ switch to enable this setting.
+
+ The following changes are based on the App Note AN3369 and
+ verified to improve memory latency using LMbench:
+
+ 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
+ 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
+ previously.
+ 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
+ Twr=15ns, and this was already the setting in DDR_MODE)
+ 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
+ Trp=15ns)
+ 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
+ Tras=40ns)
+ 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
+ Trcd=15ns)
+ 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
+ Trfc=75ns)
+ 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
+ on Tfaw=50ns)
+ 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
+ on CL=3 and WL=2).
+
+ Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit fc549c871f43933396a5b3e21d897023d4b31b8d
+Author: Michael Barkowski <michael.barkowski@freescale.com>
+Date: Thu Mar 20 13:15:28 2008 -0400
+
+ mpc8323erdb: use readable DDR config macros
+
+ Use available shift/mask macros to define DDR configuration.
+
+ Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
+ Acked-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 89c7784ed90ba50301eec521144f95111e472906
+Author: Timur Tabi <timur@freescale.com>
+Date: Fri Feb 8 13:15:55 2008 -0600
+
+ 83xx: Add Vitesse VSC7385 firmware uploading
+
+ Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
+ the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
+ Cleaned up the board header files to make selecting the VSC7385 easier to
+ control.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+ Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit b55d98c6d5b8694e560a0e727b14cb6921d7cfcc
+Author: Timur Tabi <timur@freescale.com>
+Date: Fri Feb 8 13:15:54 2008 -0600
+
+ NET: Add Vitesse VSC7385 firmware uploading
+
+ The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
+ and other boards. A small firwmare must be uploaded to its on-board memory
+ before it can be enabled. This patch adds the code which uploads firmware
+ (but not the firmware itself).
+
+ Previously, this feature was provided by a U-Boot application that was
+ made available only on Freescale BSPs. The VSC7385 firmware must still
+ be obtained separately, but at least there is no longer a need for a separate
+ application.
+
+ Signed-off-by: Timur Tabi <timur@freescale.com>
+ Acked-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit aa6f6d171a1f9f46ee4f03ad6acb97a6bfb71855
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Mar 26 00:52:10 2008 +0100
+
+ Coding Style cleanyp; update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+