armv8: fsl-layerscape: Add back L3 flushing for all exception levels

CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.

Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 5ff01a0e1b2cec2cdff67d5c5a64fb934b202c9e..fa93096c688c1ee3d52e02181d76c81580b1e72d 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -396,9 +396,6 @@ ENTRY(__asm_flush_l3_dcache)
        mov     x29, lr
        mov     x8, #0
 
        mov     x29, lr
        mov     x8, #0
 

-       switch_el x0, 1f, 100f, 100f    /* skip if not in EL3 */
-
-1:

        dsb     sy
        mov     x0, #0x1                /* HNFPSTAT_SFONLY */
        bl      hnf_set_pstate
        dsb     sy
        mov     x0, #0x1                /* HNFPSTAT_SFONLY */
        bl      hnf_set_pstate


@@ -416,7 +413,6 @@ ENTRY(__asm_flush_l3_dcache)
        bl      hnf_pstate_poll
        cbz     x0, 1f
        add     x8, x8, #0x2
        bl      hnf_pstate_poll
        cbz     x0, 1f
        add     x8, x8, #0x2

-100:

 1:
        mov     x0, x8
        mov     lr, x29
 1:
        mov     x0, x8
        mov     lr, x29