On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
/* Prepare to adjust MTRRs */
void mtrr_open(struct mtrr_state *state)
{
/* Prepare to adjust MTRRs */
void mtrr_open(struct mtrr_state *state)
{
+ if (!gd->arch.has_mtrr)
+ return;
+
state->enable_cache = dcache_status();
if (state->enable_cache)
state->enable_cache = dcache_status();
if (state->enable_cache)
/* Clean up after adjusting MTRRs, and enable them */
void mtrr_close(struct mtrr_state *state)
{
/* Clean up after adjusting MTRRs, and enable them */
void mtrr_close(struct mtrr_state *state)
{
+ if (!gd->arch.has_mtrr)
+ return;
+
wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
if (state->enable_cache)
enable_caches();
wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
if (state->enable_cache)
enable_caches();
+ if (!gd->arch.has_mtrr)
+ return -ENOSYS;
+
mtrr_open(&state);
for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) {
mask = ~(req->size - 1);
mtrr_open(&state);
for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) {
mask = ~(req->size - 1);
struct mtrr_request *req;
uint64_t mask;
struct mtrr_request *req;
uint64_t mask;
+ if (!gd->arch.has_mtrr)
+ return -ENOSYS;
+
if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
return -ENOSPC;
req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
return -ENOSPC;
req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
*
* @state: Structure from mtrr_open()
*/
*
* @state: Structure from mtrr_open()
*/
void mtrr_close(struct mtrr_state *state);
/**
void mtrr_close(struct mtrr_state *state);
/**
* @type: Requested type (MTRR_TYPE_)
* @start: Start address
* @size: Size
* @type: Requested type (MTRR_TYPE_)
* @start: Start address
* @size: Size
+ *
+ * @return: 0 on success, non-zero on failure
*/
int mtrr_add_request(int type, uint64_t start, uint64_t size);
*/
int mtrr_add_request(int type, uint64_t start, uint64_t size);
* It must be called with caches disabled.
*
* @do_caches: true if caches are currently on
* It must be called with caches disabled.
*
* @do_caches: true if caches are currently on
+ *
+ * @return: 0 on success, non-zero on failure
*/
int mtrr_commit(bool do_caches);
*/
int mtrr_commit(bool do_caches);
#include <common.h>
#include <fdtdec.h>
#include <spi.h>
#include <common.h>
#include <fdtdec.h>
#include <spi.h>
#include <asm/mtrr.h>
#include <asm/sections.h>
#include <asm/mtrr.h>
#include <asm/sections.h>
int ret;
ret = mtrr_commit(false);
int ret;
ret = mtrr_commit(false);
+ /* If MTRR MSR is not implemented by the processor, just ignore it */
+ if (ret && ret != -ENOSYS)
return ret;
#endif
/* Initialise the CPU cache(s) */
return ret;
#endif
/* Initialise the CPU cache(s) */