- regmap_update_bits(max98927->regmap,
- MAX98927_R0021_PCM_MASTER_MODE,
- MAX98927_PCM_MASTER_MODE_MASK,
- mode);
+ regmap_update_bits(max98927->regmap, MAX98927_R0021_PCM_MASTER_MODE,
+ MAX98927_PCM_MASTER_MODE_MASK, mode);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
- regmap_update_bits(max98927->regmap,
- MAX98927_R0020_PCM_MODE_CFG,
- MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE,
- invert);
+ regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
+ MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE, invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
if (!use_pdm) {
/* pcm channel configuration */
if (!use_pdm) {
/* pcm channel configuration */
- regmap_update_bits(max98927->regmap,
- MAX98927_R0018_PCM_RX_EN_A,
- MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
- MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
+ regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
+ MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
+ MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
regmap_update_bits(max98927->regmap,
regmap_update_bits(max98927->regmap,
- MAX98927_R0020_PCM_MODE_CFG,
- MAX98927_PCM_MODE_CFG_FORMAT_MASK,
- format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
+ MAX98927_R0020_PCM_MODE_CFG,
+ MAX98927_PCM_MODE_CFG_FORMAT_MASK,
+ format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
- regmap_update_bits(max98927->regmap,
- MAX98927_R003B_SPK_SRC_SEL,
- MAX98927_SPK_SRC_MASK, 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
+ MAX98927_SPK_SRC_MASK, 0);
- regmap_update_bits(max98927->regmap,
- MAX98927_R0035_PDM_RX_CTRL,
- MAX98927_PDM_RX_EN_MASK, 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
+ MAX98927_PDM_RX_EN_MASK, 0);
} else {
/* pdm channel configuration */
} else {
/* pdm channel configuration */
- regmap_update_bits(max98927->regmap,
- MAX98927_R0035_PDM_RX_CTRL,
- MAX98927_PDM_RX_EN_MASK, 1);
+ regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
+ MAX98927_PDM_RX_EN_MASK, 1);
- regmap_update_bits(max98927->regmap,
- MAX98927_R003B_SPK_SRC_SEL,
- MAX98927_SPK_SRC_MASK, 3);
+ regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
+ MAX98927_SPK_SRC_MASK, 3);
- regmap_update_bits(max98927->regmap,
- MAX98927_R0018_PCM_RX_EN_A,
- MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
+ MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
+ 0);
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
return -EINVAL;
}
regmap_update_bits(max98927->regmap,
- MAX98927_R0021_PCM_MASTER_MODE,
- MAX98927_PCM_MASTER_MODE_MCLK_MASK,
- i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
+ MAX98927_R0021_PCM_MASTER_MODE,
+ MAX98927_PCM_MASTER_MODE_MCLK_MASK,
+ i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
}
if (!max98927->tdm_mode) {
}
if (!max98927->tdm_mode) {
}
regmap_update_bits(max98927->regmap,
}
regmap_update_bits(max98927->regmap,
- MAX98927_R0022_PCM_CLK_SETUP,
- MAX98927_PCM_CLK_SETUP_BSEL_MASK,
- value);
+ MAX98927_R0022_PCM_CLK_SETUP,
+ MAX98927_PCM_CLK_SETUP_BSEL_MASK, value);
max98927->ch_size = snd_pcm_format_width(params_format(params));
max98927->ch_size = snd_pcm_format_width(params_format(params));
- regmap_update_bits(max98927->regmap,
- MAX98927_R0020_PCM_MODE_CFG,
- MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
+ regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
+ MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(component->dev, "format supported %d",
params_format(params));
dev_dbg(component->dev, "format supported %d",
params_format(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
- regmap_update_bits(max98927->regmap,
- MAX98927_R0023_PCM_SR_SETUP1,
- MAX98927_PCM_SR_SET1_SR_MASK,
- sampling_rate);
- regmap_update_bits(max98927->regmap,
- MAX98927_R0024_PCM_SR_SETUP2,
- MAX98927_PCM_SR_SET2_SR_MASK,
- sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
+ regmap_update_bits(max98927->regmap, MAX98927_R0023_PCM_SR_SETUP1,
+ MAX98927_PCM_SR_SET1_SR_MASK, sampling_rate);
+ regmap_update_bits(max98927->regmap, MAX98927_R0024_PCM_SR_SETUP2,
+ MAX98927_PCM_SR_SET2_SR_MASK,
+ sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
/* set sampling rate of IV */
if (max98927->interleave_mode &&
sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
regmap_update_bits(max98927->regmap,
/* set sampling rate of IV */
if (max98927->interleave_mode &&
sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
regmap_update_bits(max98927->regmap,
- MAX98927_R0024_PCM_SR_SETUP2,
- MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
- sampling_rate - 3);
+ MAX98927_R0024_PCM_SR_SETUP2,
+ MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
+ sampling_rate - 3);
else
regmap_update_bits(max98927->regmap,
else
regmap_update_bits(max98927->regmap,
- MAX98927_R0024_PCM_SR_SETUP2,
- MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
- sampling_rate);
+ MAX98927_R0024_PCM_SR_SETUP2,
+ MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
+ sampling_rate);
return max98927_set_clock(max98927, params);
err:
return -EINVAL;
return max98927_set_clock(max98927, params);
err:
return -EINVAL;
- regmap_update_bits(max98927->regmap,
- MAX98927_R0022_PCM_CLK_SETUP,
- MAX98927_PCM_CLK_SETUP_BSEL_MASK,
- bsel);
+ regmap_update_bits(max98927->regmap, MAX98927_R0022_PCM_CLK_SETUP,
+ MAX98927_PCM_CLK_SETUP_BSEL_MASK, bsel);
/* Channel size configuration */
switch (slot_width) {
/* Channel size configuration */
switch (slot_width) {
- regmap_update_bits(max98927->regmap,
- MAX98927_R0020_PCM_MODE_CFG,
- MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
+ regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
+ MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
/* Rx slot configuration */
- regmap_write(max98927->regmap,
- MAX98927_R0018_PCM_RX_EN_A,
- rx_mask & 0xFF);
- regmap_write(max98927->regmap,
- MAX98927_R0019_PCM_RX_EN_B,
- (rx_mask & 0xFF00) >> 8);
+ regmap_write(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
+ rx_mask & 0xFF);
+ regmap_write(max98927->regmap, MAX98927_R0019_PCM_RX_EN_B,
+ (rx_mask & 0xFF00) >> 8);
/* Tx slot configuration */
/* Tx slot configuration */
- regmap_write(max98927->regmap,
- MAX98927_R001A_PCM_TX_EN_A,
- tx_mask & 0xFF);
- regmap_write(max98927->regmap,
- MAX98927_R001B_PCM_TX_EN_B,
- (tx_mask & 0xFF00) >> 8);
+ regmap_write(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
+ tx_mask & 0xFF);
+ regmap_write(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
+ (tx_mask & 0xFF00) >> 8);
/* Tx slot Hi-Z configuration */
/* Tx slot Hi-Z configuration */
- regmap_write(max98927->regmap,
- MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
- ~tx_mask & 0xFF);
- regmap_write(max98927->regmap,
- MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
- (~tx_mask & 0xFF00) >> 8);
+ regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
+ ~tx_mask & 0xFF);
+ regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
+ (~tx_mask & 0xFF00) >> 8);
max98927->tdm_mode = false;
break;
case SND_SOC_DAPM_POST_PMU:
max98927->tdm_mode = false;
break;
case SND_SOC_DAPM_POST_PMU:
- regmap_update_bits(max98927->regmap,
- MAX98927_R003A_AMP_EN,
- MAX98927_AMP_EN_MASK, 1);
- regmap_update_bits(max98927->regmap,
- MAX98927_R00FF_GLOBAL_SHDN,
- MAX98927_GLOBAL_EN_MASK, 1);
+ regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
+ MAX98927_AMP_EN_MASK, 1);
+ regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
+ MAX98927_GLOBAL_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
break;
case SND_SOC_DAPM_POST_PMD:
- regmap_update_bits(max98927->regmap,
- MAX98927_R00FF_GLOBAL_SHDN,
- MAX98927_GLOBAL_EN_MASK, 0);
- regmap_update_bits(max98927->regmap,
- MAX98927_R003A_AMP_EN,
- MAX98927_AMP_EN_MASK, 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
+ MAX98927_GLOBAL_EN_MASK, 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
+ MAX98927_AMP_EN_MASK, 0);
break;
default:
return 0;
break;
default:
return 0;
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
- MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
- 3, max98927_switch_text);
+ MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 3,
+ max98927_switch_text);
static const struct snd_kcontrol_new max98927_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_kcontrol_new max98927_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
- 0, 0, max98927_dac_event,
- SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ 0, 0, max98927_dac_event,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
- &max98927_dai_controls),
+ &max98927_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
- MAX98927_R003E_MEAS_EN, 0, 0),
+ MAX98927_R003E_MEAS_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
- MAX98927_R003E_MEAS_EN, 1, 0),
+ MAX98927_R003E_MEAS_EN, 1, 0),
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
};
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
};
max98927_current_limit_text);
static const struct snd_kcontrol_new max98927_snd_controls[] = {
max98927_current_limit_text);
static const struct snd_kcontrol_new max98927_snd_controls[] = {
- SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN,
- 0, 6, 0,
- max98927_spk_tlv),
+ SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN, 0, 6, 0,
+ max98927_spk_tlv),
SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
- 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
- max98927_digital_tlv),
+ 0, (1 << MAX98927_AMP_VOL_WIDTH) - 1, 0,
+ max98927_digital_tlv),
SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
- MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
+ MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
- MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
- SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL,
- MAX98927_DRE_EN_SHIFT, 1, 0),
+ MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
+ SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL, MAX98927_DRE_EN_SHIFT,
+ 1, 0),
SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
- MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
+ MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
SOC_ENUM("Current Limit", max98927_current_limit),
};
SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
SOC_ENUM("Current Limit", max98927_current_limit),
};
max98927->component = component;
/* Software Reset */
max98927->component = component;
/* Software Reset */
- regmap_write(max98927->regmap,
- MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
+ regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
+ MAX98927_SOFT_RESET);
/* IV default slot configuration */
/* IV default slot configuration */
- regmap_write(max98927->regmap,
- MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
- 0xFF);
- regmap_write(max98927->regmap,
- MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
- 0xFF);
- regmap_write(max98927->regmap,
- MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
- 0x80);
- regmap_write(max98927->regmap,
- MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
- 0x1);
+ regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0xFF);
+ regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0xFF);
+ regmap_write(max98927->regmap, MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
+ 0x80);
+ regmap_write(max98927->regmap, MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
+ 0x1);
/* Set inital volume (+13dB) */
/* Set inital volume (+13dB) */
- regmap_write(max98927->regmap,
- MAX98927_R0036_AMP_VOL_CTRL,
- 0x38);
- regmap_write(max98927->regmap,
- MAX98927_R003C_SPK_GAIN,
- 0x05);
+ regmap_write(max98927->regmap, MAX98927_R0036_AMP_VOL_CTRL, 0x38);
+ regmap_write(max98927->regmap, MAX98927_R003C_SPK_GAIN, 0x05);
- regmap_write(max98927->regmap,
- MAX98927_R0037_AMP_DSP_CFG,
- 0x03);
+ regmap_write(max98927->regmap, MAX98927_R0037_AMP_DSP_CFG, 0x03);
/* Enable IMON VMON DC blocker */
/* Enable IMON VMON DC blocker */
- regmap_write(max98927->regmap,
- MAX98927_R003F_MEAS_DSP_CFG,
- 0xF7);
+ regmap_write(max98927->regmap, MAX98927_R003F_MEAS_DSP_CFG, 0xF7);
/* Boost Output Voltage & Current limit */
/* Boost Output Voltage & Current limit */
- regmap_write(max98927->regmap,
- MAX98927_R0040_BOOST_CTRL0,
- 0x1C);
- regmap_write(max98927->regmap,
- MAX98927_R0042_BOOST_CTRL1,
- 0x3E);
+ regmap_write(max98927->regmap, MAX98927_R0040_BOOST_CTRL0, 0x1C);
+ regmap_write(max98927->regmap, MAX98927_R0042_BOOST_CTRL1, 0x3E);
/* Measurement ADC config */
/* Measurement ADC config */
- regmap_write(max98927->regmap,
- MAX98927_R0043_MEAS_ADC_CFG,
- 0x04);
- regmap_write(max98927->regmap,
- MAX98927_R0044_MEAS_ADC_BASE_MSB,
- 0x00);
- regmap_write(max98927->regmap,
- MAX98927_R0045_MEAS_ADC_BASE_LSB,
- 0x24);
+ regmap_write(max98927->regmap, MAX98927_R0043_MEAS_ADC_CFG, 0x04);
+ regmap_write(max98927->regmap, MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x00);
+ regmap_write(max98927->regmap, MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x24);
- regmap_write(max98927->regmap,
- MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
- 0x06);
+ regmap_write(max98927->regmap, MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
+ 0x06);
/* Envelope Tracking configuration */
/* Envelope Tracking configuration */
- regmap_write(max98927->regmap,
- MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
- 0x08);
- regmap_write(max98927->regmap,
- MAX98927_R0086_ENV_TRACK_CTRL,
- 0x01);
- regmap_write(max98927->regmap,
- MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
- 0x10);
+ regmap_write(max98927->regmap, MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
+ 0x08);
+ regmap_write(max98927->regmap, MAX98927_R0086_ENV_TRACK_CTRL, 0x01);
+ regmap_write(max98927->regmap, MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
+ 0x10);
/* voltage, current slot configuration */
/* voltage, current slot configuration */
- regmap_write(max98927->regmap,
- MAX98927_R001E_PCM_TX_CH_SRC_A,
- (max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT|
- max98927->v_l_slot)&0xFF);
+ regmap_write(max98927->regmap, MAX98927_R001E_PCM_TX_CH_SRC_A,
+ (max98927->i_l_slot << MAX98927_PCM_TX_CH_SRC_A_I_SHIFT | max98927->v_l_slot) & 0xFF);
if (max98927->v_l_slot < 8) {
regmap_update_bits(max98927->regmap,
if (max98927->v_l_slot < 8) {
regmap_update_bits(max98927->regmap,
- MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
- 1 << max98927->v_l_slot, 0);
- regmap_update_bits(max98927->regmap,
- MAX98927_R001A_PCM_TX_EN_A,
- 1 << max98927->v_l_slot,
- 1 << max98927->v_l_slot);
+ MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
+ 1 << max98927->v_l_slot, 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
+ 1 << max98927->v_l_slot,
+ 1 << max98927->v_l_slot);
} else {
regmap_update_bits(max98927->regmap,
} else {
regmap_update_bits(max98927->regmap,
- MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
- 1 << (max98927->v_l_slot - 8), 0);
- regmap_update_bits(max98927->regmap,
- MAX98927_R001B_PCM_TX_EN_B,
- 1 << (max98927->v_l_slot - 8),
- 1 << (max98927->v_l_slot - 8));
+ MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
+ 1 << (max98927->v_l_slot - 8), 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
+ 1 << (max98927->v_l_slot - 8),
+ 1 << (max98927->v_l_slot - 8));
}
if (max98927->i_l_slot < 8) {
regmap_update_bits(max98927->regmap,
}
if (max98927->i_l_slot < 8) {
regmap_update_bits(max98927->regmap,
- MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
- 1 << max98927->i_l_slot, 0);
- regmap_update_bits(max98927->regmap,
- MAX98927_R001A_PCM_TX_EN_A,
- 1 << max98927->i_l_slot,
- 1 << max98927->i_l_slot);
+ MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
+ 1 << max98927->i_l_slot, 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
+ 1 << max98927->i_l_slot,
+ 1 << max98927->i_l_slot);
} else {
regmap_update_bits(max98927->regmap,
} else {
regmap_update_bits(max98927->regmap,
- MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
- 1 << (max98927->i_l_slot - 8), 0);
- regmap_update_bits(max98927->regmap,
- MAX98927_R001B_PCM_TX_EN_B,
- 1 << (max98927->i_l_slot - 8),
- 1 << (max98927->i_l_slot - 8));
+ MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
+ 1 << (max98927->i_l_slot - 8), 0);
+ regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
+ 1 << (max98927->i_l_slot - 8),
+ 1 << (max98927->i_l_slot - 8));
}
/* Set interleave mode */
if (max98927->interleave_mode)
regmap_update_bits(max98927->regmap,
}
/* Set interleave mode */
if (max98927->interleave_mode)
regmap_update_bits(max98927->regmap,
- MAX98927_R001F_PCM_TX_CH_SRC_B,
- MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
- MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
+ MAX98927_R001F_PCM_TX_CH_SRC_B,
+ MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
+ MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
{
struct max98927_priv *max98927 = dev_get_drvdata(dev);
{
struct max98927_priv *max98927 = dev_get_drvdata(dev);
- regmap_write(max98927->regmap,
- MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
+ regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
+ MAX98927_SOFT_RESET);
regcache_cache_only(max98927->regmap, false);
regcache_sync(max98927->regmap);
return 0;
regcache_cache_only(max98927->regmap, false);
regcache_sync(max98927->regmap);
return 0;
int reg = 0;
struct max98927_priv *max98927 = NULL;
int reg = 0;
struct max98927_priv *max98927 = NULL;
- max98927 = devm_kzalloc(&i2c->dev,
- sizeof(*max98927), GFP_KERNEL);
-
+ max98927 = devm_kzalloc(&i2c->dev, sizeof(*max98927), GFP_KERNEL);
if (!max98927) {
ret = -ENOMEM;
return ret;
if (!max98927) {
ret = -ENOMEM;
return ret;
"Failed to allocate regmap: %d\n", ret);
return ret;
}
"Failed to allocate regmap: %d\n", ret);
return ret;
}
-
- max98927->reset_gpio
- = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_HIGH);
+
+ max98927->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset",
+ GPIOD_OUT_HIGH);
if (IS_ERR(max98927->reset_gpio)) {
ret = PTR_ERR(max98927->reset_gpio);
return dev_err_probe(&i2c->dev, ret, "failed to request GPIO reset pin");
if (IS_ERR(max98927->reset_gpio)) {
ret = PTR_ERR(max98927->reset_gpio);
return dev_err_probe(&i2c->dev, ret, "failed to request GPIO reset pin");
}
/* Check Revision ID */
}
/* Check Revision ID */
- ret = regmap_read(max98927->regmap,
- MAX98927_R01FF_REV_ID, ®);
+ ret = regmap_read(max98927->regmap, MAX98927_R01FF_REV_ID, ®);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
{
struct max98927_priv *max98927 = i2c_get_clientdata(i2c);
{
struct max98927_priv *max98927 = i2c_get_clientdata(i2c);
- if (max98927->reset_gpio) {
+ if (max98927->reset_gpio)
gpiod_set_value_cansleep(max98927->reset_gpio, 1);
gpiod_set_value_cansleep(max98927->reset_gpio, 1);
}
static const struct i2c_device_id max98927_i2c_id[] = {
}
static const struct i2c_device_id max98927_i2c_id[] = {
projects / platform / kernel / linux-starfive.git / commitdiff