thunderbolt: Pass CL state bitmask to tb_port_clx_supported()

Instead of testing just a single CL state we can pass a bitmask of
states to check. This makes it simpler for callers of the function.

We also add a check for CL2 even though not fully supported by the
driver yet.

Suggested-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index deefc92c7c60468dc3f133f8be9f7032119b9965..0671f5361b5b86822353ebdc9276caabc24ef7a5 100644 (file)
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -1259,9 +1259,9 @@ static int tb_port_pm_secondary_disable(struct tb_port *port)
 }
 
 /* Called for USB4 or Titan Ridge routers only */
 }
 
 /* Called for USB4 or Titan Ridge routers only */

-static bool tb_port_clx_supported(struct tb_port *port, enum tb_clx clx)
+static bool tb_port_clx_supported(struct tb_port *port, unsigned int clx_mask)

 {
 {

-       u32 mask, val;
+       u32 val, mask = 0;

        bool ret;
 
        /* Don't enable CLx in case of two single-lane links */
        bool ret;
 
        /* Don't enable CLx in case of two single-lane links */


@@ -1279,17 +1279,12 @@ static bool tb_port_clx_supported(struct tb_port *port, enum tb_clx clx)
                return false;
        }
 
                return false;
        }
 

-       switch (clx) {
-       case TB_CL1:
+       if (clx_mask & TB_CL1) {

                /* CL0s and CL1 are enabled and supported together */
                /* CL0s and CL1 are enabled and supported together */

-               mask = LANE_ADP_CS_0_CL0S_SUPPORT | LANE_ADP_CS_0_CL1_SUPPORT;
-               break;
-
-       /* For now we support only CL0s and CL1. Not CL2 */
-       case TB_CL2:
-       default:
-               return false;
+               mask |= LANE_ADP_CS_0_CL0S_SUPPORT | LANE_ADP_CS_0_CL1_SUPPORT;

        }
        }

+       if (clx_mask & TB_CL2)
+               mask |= LANE_ADP_CS_0_CL2_SUPPORT;

 
        ret = tb_port_read(port, &val, TB_CFG_PORT,
                           port->cap_phy + LANE_ADP_CS_0, 1);
 
        ret = tb_port_read(port, &val, TB_CFG_PORT,
                           port->cap_phy + LANE_ADP_CS_0, 1);

diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
index 8291cabd2e9263ced886de4b2bdf988c9d0ed35d..8555ad9d7234fd447ac3bd66d58aea063121b581 100644 (file)
--- a/drivers/thunderbolt/tb.h
+++ b/drivers/thunderbolt/tb.h
@@ -113,8 +113,8 @@ struct tb_switch_tmu {
 enum tb_clx {
        TB_CLX_DISABLE,
        /* CL0s and CL1 are enabled and supported together */
 enum tb_clx {
        TB_CLX_DISABLE,
        /* CL0s and CL1 are enabled and supported together */

-       TB_CL1,
-       TB_CL2,
+       TB_CL1 = BIT(0),
+       TB_CL2 = BIT(1),

 };
 
 /**
 };
 
 /**

diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
index 16605411038830935e12920a2231bf5e72e0e200..a45f295533cd540dd570c45c8578ffe994157093 100644 (file)
--- a/drivers/thunderbolt/tb_regs.h
+++ b/drivers/thunderbolt/tb_regs.h
@@ -324,6 +324,7 @@ struct tb_regs_port_header {
 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL     0x2
 #define LANE_ADP_CS_0_CL0S_SUPPORT             BIT(26)
 #define LANE_ADP_CS_0_CL1_SUPPORT              BIT(27)
 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL     0x2
 #define LANE_ADP_CS_0_CL0S_SUPPORT             BIT(26)
 #define LANE_ADP_CS_0_CL1_SUPPORT              BIT(27)

+#define LANE_ADP_CS_0_CL2_SUPPORT              BIT(28)

 #define LANE_ADP_CS_1                          0x01
 #define LANE_ADP_CS_1_TARGET_SPEED_MASK                GENMASK(3, 0)
 #define LANE_ADP_CS_1_TARGET_SPEED_GEN3                0xc
 #define LANE_ADP_CS_1                          0x01
 #define LANE_ADP_CS_1_TARGET_SPEED_MASK                GENMASK(3, 0)
 #define LANE_ADP_CS_1_TARGET_SPEED_GEN3                0xc