binutils/
PR binutils/20337
* objdump.c (compare_symbols): For ELF, sort same value/type
symbols according to size.
ld/
* testsuite/ld-powerpc/elfv2exe.d: Update.
+2016-07-09 Alan Modra <amodra@gmail.com>
+
+ PR binutils/20337
+ * objdump.c (compare_symbols): For ELF, sort same value/type
+ symbols according to size.
+
2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
* objdump.c (dump_section_header): Rename SEC_ELF_NOREAD
2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com>
* objdump.c (dump_section_header): Rename SEC_ELF_NOREAD
+ if (bfd_get_flavour (bfd_asymbol_bfd (a)) == bfd_target_elf_flavour
+ && bfd_get_flavour (bfd_asymbol_bfd (b)) == bfd_target_elf_flavour)
+ {
+ bfd_vma asz, bsz;
+
+ asz = 0;
+ if ((a->flags & BSF_SYNTHETIC) == 0)
+ asz = ((elf_symbol_type *) a)->internal_elf_sym.st_size;
+ bsz = 0;
+ if ((b->flags & BSF_SYNTHETIC) == 0)
+ bsz = ((elf_symbol_type *) b)->internal_elf_sym.st_size;
+ if (asz != bsz)
+ return asz > bsz ? -1 : 1;
+ }
+
/* Symbols that start with '.' might be section names, so sort them
after symbols that don't start with '.'. */
if (an[0] == '.' && bn[0] != '.')
/* Symbols that start with '.' might be section names, so sort them
after symbols that don't start with '.'. */
if (an[0] == '.' && bn[0] != '.')
+2016-07-09 Alan Modra <amodra@gmail.com>
+
+ * testsuite/ld-powerpc/elfv2exe.d: Update.
+
2016-07-06 James Bowman <james.bowman@ftdichip.com>
* scripttempl/ft32.sc (__PMSIZE): Correct __PMSIZE_.
2016-07-06 James Bowman <james.bowman@ftdichip.com>
* scripttempl/ft32.sc (__PMSIZE): Correct __PMSIZE_.
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
+0+100000e0 <(f1|_start)>:
.*: (3c 40 10 02|02 10 40 3c) lis r2,4098
.*: (38 42 82 00|00 82 42 38) addi r2,r2,-32256
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\)
.*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\)
.*: (3c 40 10 02|02 10 40 3c) lis r2,4098
.*: (38 42 82 00|00 82 42 38) addi r2,r2,-32256
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (f8 21 ff e1|e1 ff 21 f8) stdu r1,-32\(r1\)
.*: (f8 01 00 30|30 00 01 f8) std r0,48\(r1\)
-.*: (4b ff ff f5|f5 ff ff 4b) bl .* <_start\+0x8>
+.*: (4b ff ff f5|f5 ff ff 4b) bl .* <(f1|_start)\+0x8>
.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
.*: (4b ff ff c5|c5 ff ff 4b) bl .*\.plt_branch\.f2>
.*: (60 00 00 00|00 00 00 60) nop
.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
.*: (4b ff ff c5|c5 ff ff 4b) bl .*\.plt_branch\.f2>
.*: (60 00 00 00|00 00 00 60) nop