spi: fsl: Use BIT macro

Replace numerical bit shift with BIT macro
in fsl_*spi.c

:%s/(1 << nr)/BIT(nr)/g
where nr = 0, 1, 2 .... 31

Cc: York Sun <yorksun@freescale.com>
Cc: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>

diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index 887edd8..c8dcb27 100644 (file)
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -24,7 +24,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */
 DECLARE_GLOBAL_DATA_PTR;
 
 /* fsl_dspi_platdata flags */

-#define DSPI_FLAG_REGMAP_ENDIAN_BIG    (1 << 0)
+#define DSPI_FLAG_REGMAP_ENDIAN_BIG    BIT(0)

 
 /* idle data value */
 #define DSPI_IDLE_VAL                  0x0
 
 /* idle data value */
 #define DSPI_IDLE_VAL                  0x0

diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c
index 375dc07..b1586d1 100644 (file)
--- a/drivers/spi/fsl_espi.c
+++ b/drivers/spi/fsl_espi.c
@@ -32,26 +32,26 @@ struct fsl_spi_slave {
 #define ESPI_MAX_CS_NUM                4
 #define ESPI_FIFO_WIDTH_BIT    32
 
 #define ESPI_MAX_CS_NUM                4
 #define ESPI_FIFO_WIDTH_BIT    32
 

-#define ESPI_EV_RNE            (1 << 9)
-#define ESPI_EV_TNF            (1 << 8)
-#define ESPI_EV_DON            (1 << 14)
-#define ESPI_EV_TXE            (1 << 15)
+#define ESPI_EV_RNE            BIT(9)
+#define ESPI_EV_TNF            BIT(8)
+#define ESPI_EV_DON            BIT(14)
+#define ESPI_EV_TXE            BIT(15)

 #define ESPI_EV_RFCNT_SHIFT    24
 #define ESPI_EV_RFCNT_MASK     (0x3f << ESPI_EV_RFCNT_SHIFT)
 
 #define ESPI_EV_RFCNT_SHIFT    24
 #define ESPI_EV_RFCNT_MASK     (0x3f << ESPI_EV_RFCNT_SHIFT)
 

-#define ESPI_MODE_EN           (1 << 31)       /* Enable interface */
+#define ESPI_MODE_EN           BIT(31) /* Enable interface */

 #define ESPI_MODE_TXTHR(x)     ((x) << 8)      /* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x)     ((x) << 0)      /* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x)         ((x) << 30)
 #define ESPI_COM_TRANLEN(x)    ((x) << 0)
 
 #define ESPI_MODE_TXTHR(x)     ((x) << 8)      /* Tx FIFO threshold */
 #define ESPI_MODE_RXTHR(x)     ((x) << 0)      /* Rx FIFO threshold */
 
 #define ESPI_COM_CS(x)         ((x) << 30)
 #define ESPI_COM_TRANLEN(x)    ((x) << 0)
 

-#define ESPI_CSMODE_CI_INACTIVEHIGH    (1 << 31)
-#define ESPI_CSMODE_CP_BEGIN_EDGCLK    (1 << 30)
-#define ESPI_CSMODE_REV_MSB_FIRST      (1 << 29)
-#define ESPI_CSMODE_DIV16              (1 << 28)
+#define ESPI_CSMODE_CI_INACTIVEHIGH    BIT(31)
+#define ESPI_CSMODE_CP_BEGIN_EDGCLK    BIT(30)
+#define ESPI_CSMODE_REV_MSB_FIRST      BIT(29)
+#define ESPI_CSMODE_DIV16              BIT(28)

 #define ESPI_CSMODE_PM(x)              ((x) << 24)
 #define ESPI_CSMODE_PM(x)              ((x) << 24)

-#define ESPI_CSMODE_POL_ASSERTED_LOW   (1 << 20)
+#define ESPI_CSMODE_POL_ASSERTED_LOW   BIT(20)

 #define ESPI_CSMODE_LEN(x)             ((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)           ((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)           ((x) << 8)
 #define ESPI_CSMODE_LEN(x)             ((x) << 16)
 #define ESPI_CSMODE_CSBEF(x)           ((x) << 12)
 #define ESPI_CSMODE_CSAFT(x)           ((x) << 8)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 868df5f..e1a0ec9 100644 (file)
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
 
 /* fsl_qspi_platdata flags */
 #define QSPI_CMD_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
 
 /* fsl_qspi_platdata flags */

-#define QSPI_FLAG_REGMAP_ENDIAN_BIG    (1 << 0)
+#define QSPI_FLAG_REGMAP_ENDIAN_BIG    BIT(0)

 
 /* default SCK frequency, unit: HZ */
 #define FSL_QSPI_DEFAULT_SCK_FREQ      50000000
 
 /* default SCK frequency, unit: HZ */
 #define FSL_QSPI_DEFAULT_SCK_FREQ      50000000


@@ -383,7 +383,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
        /* Enable the module again (enable the DDR too) */
        reg |= QSPI_MCR_DDR_EN_MASK;
        /* Enable bit 29 for imx6sx */
        /* Enable the module again (enable the DDR too) */
        reg |= QSPI_MCR_DDR_EN_MASK;
        /* Enable bit 29 for imx6sx */

-       reg |= (1 << 29);
+       reg |= BIT(29);

 
        qspi_write32(priv->flags, &regs->mcr, reg);
 }
 
        qspi_write32(priv->flags, &regs->mcr, reg);
 }