+}
+
+/*----------------------------------------------------------------------------+
+ | update_zii_ios(void).
+ +----------------------------------------------------------------------------*/
+void update_zii_ios(void)
+{
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
+ gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
+ gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
+ gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
+ gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
+ gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
+ gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
+ gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
+ gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
+ gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
+ gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
+ gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
+ gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
+ gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
+ gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_0_3_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_0_3_irq_ios(void)
+{
+ gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
+ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
+ gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
+ gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
+ gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_4_9_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_4_9_irq_ios(void)
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_a_b_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_a_b_ios(void)
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_c_d_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_c_d_ios(void)
+{
+ gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
+ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
+ gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
+ gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
+ gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
+ gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
+ gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_ebc_master_ios().
+ +----------------------------------------------------------------------------*/
+void update_ebc_master_ios(void)
+{
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_usb2_device_ios().
+ +----------------------------------------------------------------------------*/
+void update_usb2_device_ios(void)
+{
+ gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
+ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
+ gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
+ gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
+ gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_pci_patch_ios().
+ +----------------------------------------------------------------------------*/
+void update_pci_patch_ios(void)
+{
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | set_chip_gpio_configuration(unsigned char gpio_core)
+ | Put the core impacted by clock modification and sharing in reset.
+ | Config the select registers to resolve the sharing depending of the config.
+ | Configure the GPIO registers.
+ |
+ +----------------------------------------------------------------------------*/
+void set_chip_gpio_configuration(unsigned char gpio_core)
+{
+ unsigned char i=0, j=0, reg_offset = 0;
+ unsigned long gpio_reg, gpio_core_add;
+
+ /* GPIO config of the GPIOs 0 to 31 */
+ for (i=0; i<GPIO_MAX; i++, j++)
+ {
+ if (i == GPIO_MAX/2)
+ {
+ reg_offset = 4;
+ j = i-16;
+ }
+
+ gpio_core_add = gpio_tab[gpio_core][i].add;
+
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------+
+ | force_bup_core_selection.
+ +----------------------------------------------------------------------------*/
+void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
+{
+ /* Pointer invalid */
+ if (core_select_P == NULL)
+ {
+ printf("Configuration invalid pointer 1\n");
+ for (;;)
+ ;
+ }
+
+ /* L4 Selection */
+ *(core_select_P+UART_CORE0) = CORE_SELECTED;
+ *(core_select_P+UART_CORE1) = CORE_SELECTED;
+ *(core_select_P+UART_CORE2) = CORE_SELECTED;
+ *(core_select_P+UART_CORE3) = CORE_SELECTED;
+
+ /* RMII Selection */
+ *(core_select_P+RMII_SEL) = CORE_SELECTED;
+
+ /* External Interrupt 0-9 selection */
+ *(core_select_P+UIC_0_3) = CORE_SELECTED;
+ *(core_select_P+UIC_4_9) = CORE_SELECTED;
+
+ *(core_select_P+SCP_CORE) = CORE_SELECTED;
+ *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
+ *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
+ *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
+
+ *config_val_P = CONFIG_IS_VALID;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | configure_ppc440ep_pins.
+ +----------------------------------------------------------------------------*/
+void configure_ppc440ep_pins(void)
+{
+ uart_config_nb_t uart_configuration;
+ config_validity_t config_val = CONFIG_IS_INVALID;
+
+ /* Create Core Selection Table */
+ core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
+ {
+ CORE_NOT_SELECTED, /* IIC_CORE, */
+ CORE_NOT_SELECTED, /* SPC_CORE, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
+ CORE_NOT_SELECTED, /* UIC_4_9, */
+ CORE_NOT_SELECTED, /* USB2_HOST, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
+ CORE_NOT_SELECTED, /* USB2_DEVICE, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
+ CORE_NOT_SELECTED, /* USB1_DEVICE, */
+ CORE_NOT_SELECTED, /* EBC_MASTER, */
+ CORE_NOT_SELECTED, /* NAND_FLASH, */
+ CORE_NOT_SELECTED, /* UART_CORE0, */
+ CORE_NOT_SELECTED, /* UART_CORE1, */
+ CORE_NOT_SELECTED, /* UART_CORE2, */
+ CORE_NOT_SELECTED, /* UART_CORE3, */
+ CORE_NOT_SELECTED, /* MII_SEL, */
+ CORE_NOT_SELECTED, /* RMII_SEL, */
+ CORE_NOT_SELECTED, /* SMII_SEL, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
+ CORE_NOT_SELECTED, /* UIC_0_3 */
+ CORE_NOT_SELECTED, /* USB1_HOST */
+ CORE_NOT_SELECTED /* PCI_PATCH */
+ };
+
+
+ /* Table Default Initialisation + FPGA Access */
+ init_default_gpio();
+ set_chip_gpio_configuration(GPIO0);
+ set_chip_gpio_configuration(GPIO1);
+
+ /* Update Table */
+ force_bup_core_selection(ppc440ep_core_selection, &config_val);
+#if 0 /* test-only */
+ /* If we are running PIBS 1, force known configuration */
+ update_core_selection_table(ppc440ep_core_selection, &config_val);
+#endif
+
+ /*----------------------------------------------------------------------------+
+ | SDR + ios table update + fpga initialization
+ +----------------------------------------------------------------------------*/
+ unsigned long sdr0_pfc1 = 0;
+ unsigned long sdr0_usb0 = 0;
+ unsigned long sdr0_mfr = 0;
+
+ /* PCI Always selected */
+
+ /* I2C Selection */
+ if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+ iic1_selection_in_fpga();
+ }
+
+ /* SCP Selection */
+ if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+ scp_selection_in_fpga();
+ }
+
+ /* UIC 0:3 Selection */
+ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
+ {
+ update_uic_0_3_irq_ios();
+ dma_a_b_unselect_in_fpga();
+ }
+
+ /* UIC 4:9 Selection */
+ if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
+ update_uic_4_9_irq_ios();
+ }
+
+ /* DMA AB Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
+ update_dma_a_b_ios();
+ dma_a_b_selection_in_fpga();
+ }
+
+ /* DMA CD Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
+ {
+ update_dma_c_d_ios();
+ dma_c_d_selection_in_fpga();
+ }
+
+ /* EBC Master Selection */
+ if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_ebc_master_ios();
+ }
+
+ /* PCI Patch Enable */
+ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_pci_patch_ios();
+ }
+
+ /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
+ if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
+ {
+ /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
+ printf("Invalid configuration => USB2 Host selected\n");
+ for (;;)
+ ;
+ /*usb2_host_selection_in_fpga(); */
+ }
+
+ /* USB2.0 Device Selection */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ {
+ update_usb2_device_ios();
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
+
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
+ mtsdr(sdr_usb0, sdr0_usb0);
+
+ usb2_device_selection_in_fpga();
+ }
+
+ /* USB1.1 Device Selection */
+ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
+ {
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
+ mtsdr(sdr_usb0, sdr0_usb0);
+ }
+
+ /* USB1.1 Host Selection */
+ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
+ {
+ mfsdr(sdr_usb0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
+ mtsdr(sdr_usb0, sdr0_usb0);
+ }
+
+ /* NAND Flash Selection */
+ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
+ {
+ update_ndfc_ios();
+
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ SDR0_CUST0_CHIPSELGAT_EN1 );
+ /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
+ /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
+
+ ndfc_selection_in_fpga();
+ }
+ else
+ {
+ /* Set Mux on EMAC */
+ mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
+ }
+
+ /* MII Selection */
+ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
+ }
+
+ /* RMII Selection */
+ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
+ }
+
+ /* SMII Selection */
+ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios();
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
+ mtsdr(sdr_mfr, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
+ }
+
+ /* UART Selection */
+ uart_configuration = get_uart_configuration();
+ switch (uart_configuration)
+ {
+ case L1: /* L1 Selection */
+ /* UART0 8 pins Only */
+ /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
+ break;
+ case L2: /* L2 Selection */
+ /* UART0 and UART1 4 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L3: /* L3 Selection */
+ /* UART0 4 pins, UART1 and UART2 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L4: /* L4 Selection */
+ /* UART0, UART1, UART2 and UART3 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ }
+ update_uart_ios(uart_configuration);
+
+ /* UART Selection in all cases */
+ uart_selection_in_fpga(uart_configuration);
+
+ /* Packet Reject Function Available */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
+ {
+ /* Set UPR Bit in SDR0_PFC1 Register */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
+ }
+
+ /* Packet Reject Function Enable */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
+ {
+ mfsdr(sdr_mfr, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
+ mtsdr(sdr_mfr, sdr0_mfr);
+ }
+
+ /* Perform effective access to hardware */
+ mtsdr(sdr_pfc1, sdr0_pfc1);
+ set_chip_gpio_configuration(GPIO0);
+ set_chip_gpio_configuration(GPIO1);
+
+ /* USB2.0 Device Reset must be done after GPIO setting */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ usb2_device_reset_through_fpga();
+
+}