Some parts of the sunxi code cast explicitly between u32 values and pointers.
This is not a problem in practice, because all 64bit SoCs today only use the
lower 32 bits for their phyical address space. But we need to make sure that
the compiler is sure this is not an accident as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
int i;
for (i = 0; i< 4; i++)
int i;
for (i = 0; i< 4; i++)
- sid[i] = readl(SUNXI_SID_BASE + 4 * i);
+ sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i);
{
/* Try to write different values to RAM at two addresses */
writel(0, CONFIG_SYS_SDRAM_BASE);
{
/* Try to write different values to RAM at two addresses */
writel(0, CONFIG_SYS_SDRAM_BASE);
- writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
+ writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
/* Check if the same value is actually observed when reading back */
return readl(CONFIG_SYS_SDRAM_BASE) ==
/* Check if the same value is actually observed when reading back */
return readl(CONFIG_SYS_SDRAM_BASE) ==
- readl(CONFIG_SYS_SDRAM_BASE + offset);
+ readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
int id;
int init_count;
int power_on_count;
int id;
int init_count;
int power_on_count;
} sunxi_usb_phy[] = {
{
.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
} sunxi_usb_phy[] = {
{
.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
if (data) {
cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
if (data) {
- if ((u32) data->dest & 0x3) {
+ if ((u32)(long)data->dest & 0x3) {