projects
/
profile
/
ivi
/
mesa.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
1a25ebe
)
radeon/llvm: Add helper function for getting sub reg indices
author
Tom Stellard
<thomas.stellard@amd.com>
Mon, 20 Aug 2012 21:08:03 +0000
(21:08 +0000)
committer
Tom Stellard
<thomas.stellard@amd.com>
Tue, 21 Aug 2012 15:42:44 +0000
(15:42 +0000)
src/gallium/drivers/radeon/R600InstrInfo.cpp
patch
|
blob
|
history
src/gallium/drivers/radeon/R600RegisterInfo.cpp
patch
|
blob
|
history
src/gallium/drivers/radeon/R600RegisterInfo.h
patch
|
blob
|
history
diff --git
a/src/gallium/drivers/radeon/R600InstrInfo.cpp
b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index
7a8a58e
..
12b4665
100644
(file)
--- a/
src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/
src/gallium/drivers/radeon/R600InstrInfo.cpp
@@
-50,16
+50,13
@@
R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const
{
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const
{
-
- unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y,
- AMDGPU::sel_z, AMDGPU::sel_w};
-
if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
&& AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
for (unsigned i = 0; i < 4; i++) {
if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
&& AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
for (unsigned i = 0; i < 4; i++) {
+ unsigned SubRegIndex = RI.getSubRegFromChannel(i);
BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
- .addReg(RI.getSubReg(DestReg,
subRegMap[i]
), RegState::Define)
- .addReg(RI.getSubReg(SrcReg,
subRegMap[i]
))
+ .addReg(RI.getSubReg(DestReg,
SubRegIndex
), RegState::Define)
+ .addReg(RI.getSubReg(SrcReg,
SubRegIndex
))
.addReg(0) // PREDICATE_BIT
.addReg(DestReg, RegState::Define | RegState::Implicit);
}
.addReg(0) // PREDICATE_BIT
.addReg(DestReg, RegState::Define | RegState::Implicit);
}
diff --git
a/src/gallium/drivers/radeon/R600RegisterInfo.cpp
b/src/gallium/drivers/radeon/R600RegisterInfo.cpp
index
9475241
..
c2e40c7
100644
(file)
--- a/
src/gallium/drivers/radeon/R600RegisterInfo.cpp
+++ b/
src/gallium/drivers/radeon/R600RegisterInfo.cpp
@@
-112,4
+112,16
@@
const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
case MVT::i32: return AMDGPU::R600_TReg32RegisterClass;
}
}
case MVT::i32: return AMDGPU::R600_TReg32RegisterClass;
}
}
+
+unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const
+{
+ switch (Channel) {
+ default: assert(!"Invalid channel index"); return 0;
+ case 0: return AMDGPU::sel_x;
+ case 1: return AMDGPU::sel_y;
+ case 2: return AMDGPU::sel_z;
+ case 3: return AMDGPU::sel_w;
+ }
+}
+
#include "R600HwRegInfo.include"
#include "R600HwRegInfo.include"
diff --git
a/src/gallium/drivers/radeon/R600RegisterInfo.h
b/src/gallium/drivers/radeon/R600RegisterInfo.h
index
f45995d
..
60f6d53
100644
(file)
--- a/
src/gallium/drivers/radeon/R600RegisterInfo.h
+++ b/
src/gallium/drivers/radeon/R600RegisterInfo.h
@@
-46,6
+46,10
@@
struct R600RegisterInfo : public AMDGPURegisterInfo
/// type to use in the CFGStructurizer
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
/// type to use in the CFGStructurizer
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
+ /// getSubRegFromChannel - Return the sub reg enum value for the given
+ /// Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
+ unsigned getSubRegFromChannel(unsigned Channel) const;
+
private:
/// getHWRegIndexGen - Generated function returns a register's encoding
unsigned getHWRegIndexGen(unsigned reg) const;
private:
/// getHWRegIndexGen - Generated function returns a register's encoding
unsigned getHWRegIndexGen(unsigned reg) const;