mx35 iomux: correct offsets of IOMUX registers

This makes mxc_iomux_set_input() work correctly.  Previously, the
incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input()
to write to the wrong register, possibly resulting in unexpected
behaviour.

Signed-off-by: Philip Paeps <philip@paeps.cx>
Acked-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c
index a302575..698909e 100644 (file)
--- a/arch/arm/cpu/arm1136/mx35/iomux.c
+++ b/arch/arm/cpu/arm1136/mx35/iomux.c
@@ -34,8 +34,8 @@ enum iomux_reg_addr {
        IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,         /* MUX control */
        IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,     /* last MUX control */
        IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,     /* Pad control */
        IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4,         /* MUX control */
        IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324,     /* last MUX control */
        IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328,     /* Pad control */

-       IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794,     /* last Pad control */
-       IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC,   /* input select */
+       IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x7A4,     /* last Pad control */
+       IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7A8,   /* input select */

        IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,   /* last input select */
 };
 
        IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4,   /* last input select */
 };