Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
14 files changed:
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(0) >> 20)) << 1;
+ (get_ddr_freq(ctrl_num) >> 20)) << 1;
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
#include <fsl_immap.h>
#include <asm/io.h>
#include <fsl_immap.h>
#include <asm/io.h>
-unsigned int picos_to_mclk(unsigned int picos);
-
/*
* Determine Rtt value.
*
/*
* Determine Rtt value.
*
* 16 for <= 2933MT/s
* 18 for higher
*/
* 16 for <= 2933MT/s
* 18 for higher
*/
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+ const unsigned int ctrl_num)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
if (mclk_ps >= 1250)
cwl = 9;
else if (mclk_ps >= 1070)
if (mclk_ps >= 1250)
cwl = 9;
else if (mclk_ps >= 1070)
* 11 if 0.935ns > tCK >= 0.833ns
* 12 if 0.833ns > tCK >= 0.75ns
*/
* 11 if 0.935ns > tCK >= 0.833ns
* 12 if 0.833ns > tCK >= 0.75ns
*/
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+ const unsigned int ctrl_num)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
if (mclk_ps >= 2500)
cwl = 5;
if (mclk_ps >= 2500)
cwl = 5;
* Avoid writing for DDR I. The new PQ38 DDR controller
* dreams up non-zero default values to be backwards compatible.
*/
* Avoid writing for DDR I. The new PQ38 DDR controller
* dreams up non-zero default values to be backwards compatible.
*/
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_0(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const dimm_params_t *dimm_params)
{
const memctl_options_t *popts,
const dimm_params_t *dimm_params)
{
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
/* Mode register set cycle time (tMRD). */
unsigned char tmrd_mclk;
#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#endif
#ifdef CONFIG_SYS_FSL_DDR4
#endif
#ifdef CONFIG_SYS_FSL_DDR4
int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
trwt_mclk = 2;
twrt_mclk = 1;
int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
trwt_mclk = 2;
twrt_mclk = 1;
- act_pd_exit_mclk = picos_to_mclk(txp);
+ act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
pre_pd_exit_mclk = act_pd_exit_mclk;
/*
* MRS_CYC = max(tMRD, tMOD)
* tMRD = 8nCK, tMOD = max(24nCK, 15ns)
*/
pre_pd_exit_mclk = act_pd_exit_mclk;
/*
* MRS_CYC = max(tMRD, tMOD)
* tMRD = 8nCK, tMOD = max(24nCK, 15ns)
*/
- tmrd_mclk = max(24U, picos_to_mclk(15000));
+ tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
#elif defined(CONFIG_SYS_FSL_DDR3)
#elif defined(CONFIG_SYS_FSL_DDR3)
- unsigned int data_rate = get_ddr_freq(0);
+ unsigned int data_rate = get_ddr_freq(ctrl_num);
int txp;
unsigned int ip_rev;
int odt_overlap;
int txp;
unsigned int ip_rev;
int odt_overlap;
* tMRD = 4nCK (8nCK for RDIMM)
* tMOD = max(12nCK, 15ns)
*/
* tMRD = 4nCK (8nCK for RDIMM)
* tMOD = max(12nCK, 15ns)
*/
- tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000));
+ tmrd_mclk = max((unsigned int)12,
+ picos_to_mclk(ctrl_num, 15000));
} else {
/*
* MRS_CYC = tMRD
} else {
/*
* MRS_CYC = tMRD
taxpd_mclk = 1;
} else {
/* act_pd_exit_mclk = tXARD, see above */
taxpd_mclk = 1;
} else {
/* act_pd_exit_mclk = tXARD, see above */
- act_pd_exit_mclk = picos_to_mclk(txp);
+ act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
/* Mode register MR0[A12] is '1' - fast exit */
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 1;
/* Mode register MR0[A12] is '1' - fast exit */
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 1;
#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
-static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm,
- unsigned int cas_latency,
- unsigned int additive_latency)
+static void set_timing_cfg_3(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency,
+ unsigned int additive_latency)
{
/* Extended precharge to activate interval (tRP) */
unsigned int ext_pretoact = 0;
{
/* Extended precharge to activate interval (tRP) */
unsigned int ext_pretoact = 0;
/* Control Adjust */
unsigned int cntl_adj = 0;
/* Control Adjust */
unsigned int cntl_adj = 0;
- ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
- ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
- ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
+ ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
+ ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
+ ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
ext_add_lat = additive_latency >> 4;
#ifdef CONFIG_SYS_FSL_DDR4
ext_caslat = (2 * cas_latency - 1) >> 4;
ext_add_lat = additive_latency >> 4;
#ifdef CONFIG_SYS_FSL_DDR4
- ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
+ ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
- ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
+ ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
#endif
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
#endif
- ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+ ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
ddr->timing_cfg_3 = (0
(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
ddr->timing_cfg_3 = (0
}
/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
}
/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
-static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm,
- unsigned int cas_latency)
+static void set_timing_cfg_1(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency)
{
/* Precharge-to-activate interval (tRP) */
unsigned char pretoact_mclk;
{
/* Precharge-to-activate interval (tRP) */
unsigned char pretoact_mclk;
1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
#endif
1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
#endif
- pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
- acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
- acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
+ pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
+ acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
+ acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
/*
* Translate CAS Latency to a DDR controller field value:
/*
* Translate CAS Latency to a DDR controller field value:
#endif
#ifdef CONFIG_SYS_FSL_DDR4
#endif
#ifdef CONFIG_SYS_FSL_DDR4
- refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
- wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
- acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
- wrtord_mclk = max(2U, picos_to_mclk(2500));
+ refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
+ wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+ acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
+ wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
#else
if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
#else
- refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
- wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
- acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
- wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+ refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
+ wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+ acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
+ wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
else
}
/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
}
/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
-static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm,
- unsigned int cas_latency,
- unsigned int additive_latency)
+static void set_timing_cfg_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm,
+ unsigned int cas_latency,
+ unsigned int additive_latency)
{
/* Additive latency */
unsigned char add_lat_mclk;
{
/* Additive latency */
unsigned char add_lat_mclk;
/* Window for four activates (tFAW) */
unsigned short four_act;
#ifdef CONFIG_SYS_FSL_DDR3
/* Window for four activates (tFAW) */
unsigned short four_act;
#ifdef CONFIG_SYS_FSL_DDR3
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#endif
/* FIXME add check that this must be less than acttorw_mclk */
#endif
/* FIXME add check that this must be less than acttorw_mclk */
#elif defined(CONFIG_SYS_FSL_DDR2)
wr_lat = cas_latency - 1;
#else
#elif defined(CONFIG_SYS_FSL_DDR2)
wr_lat = cas_latency - 1;
#else
- wr_lat = compute_cas_write_latency();
+ wr_lat = compute_cas_write_latency(ctrl_num);
#endif
#ifdef CONFIG_SYS_FSL_DDR4
#endif
#ifdef CONFIG_SYS_FSL_DDR4
- rd_to_pre = picos_to_mclk(7500);
+ rd_to_pre = picos_to_mclk(ctrl_num, 7500);
- rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+ rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
#endif
/*
* JEDEC has some min requirements for tRTP
#endif
/*
* JEDEC has some min requirements for tRTP
wr_data_delay = popts->write_data_delay;
#ifdef CONFIG_SYS_FSL_DDR4
cpo = 0;
wr_data_delay = popts->write_data_delay;
#ifdef CONFIG_SYS_FSL_DDR4
cpo = 0;
- cke_pls = max(3U, picos_to_mclk(5000));
+ cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* cke pulse = max(3nCK, 7.5ns) for DDR3-800
* max(3nCK, 5.625ns) for DDR3-1066, 1333
* max(3nCK, 5ns) for DDR3-1600, 1866, 2133
*/
#elif defined(CONFIG_SYS_FSL_DDR3)
/*
* cke pulse = max(3nCK, 7.5ns) for DDR3-800
* max(3nCK, 5.625ns) for DDR3-1066, 1333
* max(3nCK, 5ns) for DDR3-1600, 1866, 2133
*/
- cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
- (mclk_ps > 1245 ? 5625 : 5000)));
+ cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
+ (mclk_ps > 1245 ? 5625 : 5000)));
#else
cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
#endif
#else
cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
#endif
- four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
+ four_act = picos_to_mclk(ctrl_num,
+ popts->tfaw_window_four_activates_ps);
ddr->timing_cfg_2 = (0
| ((add_lat_mclk & 0xf) << 28)
ddr->timing_cfg_2 = (0
| ((add_lat_mclk & 0xf) << 28)
}
/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
}
/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
-static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const unsigned int unq_mrs_en)
{
const memctl_options_t *popts,
const unsigned int unq_mrs_en)
{
#endif
#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
#endif
#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
- slow = get_ddr_freq(0) < 1249000000;
+ slow = get_ddr_freq(ctrl_num) < 1249000000;
#endif
if (popts->registered_dimm_en) {
#endif
if (popts->registered_dimm_en) {
#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
unsigned int wr_crc = 0; /* Disable */
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
unsigned int wr_crc = 0; /* Disable */
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
- unsigned int cwl = compute_cas_write_latency() - 9;
+ unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
unsigned int mpr = 0; /* serial */
unsigned int wc_lat;
unsigned int mpr = 0; /* serial */
unsigned int wc_lat;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
if (popts->rtt_override)
rtt_wr = popts->rtt_wr_override_value;
if (popts->rtt_override)
rtt_wr = popts->rtt_wr_override_value;
}
#elif defined(CONFIG_SYS_FSL_DDR3)
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
}
#elif defined(CONFIG_SYS_FSL_DDR3)
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
unsigned int asr = 0; /* auto self-refresh disable */
unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
unsigned int srt = 0; /* self-refresh temerature, normal range */
unsigned int asr = 0; /* auto self-refresh disable */
- unsigned int cwl = compute_cas_write_latency() - 5;
+ unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
unsigned int pasr = 0; /* partial array self refresh disable */
if (popts->rtt_override)
unsigned int pasr = 0; /* partial array self refresh disable */
if (popts->rtt_override)
#else /* for DDR2 and DDR1 */
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
#else /* for DDR2 and DDR1 */
/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
}
/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
}
/* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
-static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
const unsigned int unq_mrs_en)
int i;
unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
int i;
unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
- unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
+ unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
#endif
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
#endif
/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
-static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts,
- const common_timing_params_t *common_dimm)
+static void set_ddr_sdram_interval(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const memctl_options_t *popts,
+ const common_timing_params_t *common_dimm)
{
unsigned int refint; /* Refresh interval */
unsigned int bstopre; /* Precharge interval */
{
unsigned int refint; /* Refresh interval */
unsigned int bstopre; /* Precharge interval */
- refint = picos_to_mclk(common_dimm->refresh_rate_ps);
+ refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
bstopre = popts->bstopre;
bstopre = popts->bstopre;
#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
#ifdef CONFIG_SYS_FSL_DDR4
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
* 1=fast exit DLL on (tXP)
*/
* 1=fast exit DLL on (tXP)
*/
- wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+ wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
if (wr_mclk <= 24) {
wr = wr_table[wr_mclk - 10];
} else {
if (wr_mclk <= 24) {
wr = wr_table[wr_mclk - 10];
} else {
#elif defined(CONFIG_SYS_FSL_DDR3)
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
#elif defined(CONFIG_SYS_FSL_DDR3)
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
- wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+ wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
if (wr_mclk <= 16) {
wr = wr_table[wr_mclk - 5];
} else {
if (wr_mclk <= 16) {
wr = wr_table[wr_mclk - 5];
} else {
#else /* !CONFIG_SYS_FSL_DDR3 */
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
#else /* !CONFIG_SYS_FSL_DDR3 */
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
#if defined(CONFIG_SYS_FSL_DDR1)
wr = 0; /* Historical */
#elif defined(CONFIG_SYS_FSL_DDR2)
#if defined(CONFIG_SYS_FSL_DDR1)
wr = 0; /* Historical */
#elif defined(CONFIG_SYS_FSL_DDR2)
- wr = picos_to_mclk(common_dimm->twr_ps);
+ wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
#endif
dll_res = 0;
mode = 0;
#endif
dll_res = 0;
mode = 0;
debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
}
debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
}
-static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
- const common_timing_params_t *common_dimm)
+static void set_timing_cfg_7(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
+ const common_timing_params_t *common_dimm)
{
unsigned int txpr, tcksre, tcksrx;
unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
{
unsigned int txpr, tcksre, tcksrx;
unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
- txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
- tcksre = max(5U, picos_to_mclk(10000));
- tcksrx = max(5U, picos_to_mclk(10000));
+ txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
+ tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
+ tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
par_lat = 0;
cs_to_cmd = 0;
par_lat = 0;
cs_to_cmd = 0;
debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
}
debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
}
-static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_8(const unsigned int ctrl_num,
+ fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency)
{
unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency)
{
unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
- unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
+ unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
((ddr->timing_cfg_2 & 0x00040000) >> 14);
unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
((ddr->timing_cfg_2 & 0x00040000) >> 14);
- acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
- wrtord_bg = max(4U, picos_to_mclk(7500));
+ acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
+ wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
if (popts->otf_burst_chop_en)
wrtord_bg += 2;
if (popts->otf_burst_chop_en)
wrtord_bg += 2;
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+ const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_params,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_params,
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_SYS_FSL_DDR1)
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_SYS_FSL_DDR1)
- set_timing_cfg_0(ddr, popts, dimm_params);
+ set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
- set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+ set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
- set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
- set_timing_cfg_2(ddr, popts, common_dimm,
- cas_latency, additive_latency);
+ set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
+ cas_latency, additive_latency);
set_ddr_cdr1(ddr, popts);
set_ddr_cdr2(ddr, popts);
set_ddr_cdr1(ddr, popts);
set_ddr_cdr2(ddr, popts);
if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
ddr->debug[18] = popts->cswl_override;
if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
ddr->debug[18] = popts->cswl_override;
- set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
- set_ddr_sdram_mode(ddr, popts, common_dimm,
- cas_latency, additive_latency, unq_mrs_en);
- set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+ set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
+ set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
+ cas_latency, additive_latency, unq_mrs_en);
+ set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
#ifdef CONFIG_SYS_FSL_DDR4
set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
#ifdef CONFIG_SYS_FSL_DDR4
set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
- set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
+ set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
- set_ddr_sdram_interval(ddr, popts, common_dimm);
+ set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
#ifdef CONFIG_SYS_FSL_DDR4
set_ddr_sdram_cfg_3(ddr, popts);
set_timing_cfg_6(ddr);
#ifdef CONFIG_SYS_FSL_DDR4
set_ddr_sdram_cfg_3(ddr, popts);
set_timing_cfg_6(ddr);
- set_timing_cfg_7(ddr, common_dimm);
- set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
+ set_timing_cfg_7(ctrl_num, ddr, common_dimm);
+ set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
set_timing_cfg_9(ddr);
set_ddr_dq_mapping(ddr, dimm_params);
#endif
set_timing_cfg_9(ddr);
set_ddr_dq_mapping(ddr, dimm_params);
#endif
*
* FIXME: use #define for the retvals
*/
*
* FIXME: use #define for the retvals
*/
-unsigned int
-ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const ddr1_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
- pdimm->caslat_lowest_derated
- = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
+ pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
+ get_memory_clk_period_ps(ctrl_num));
/* Compute timing parameters */
pdimm->trcd_ps = spd->trcd * 250;
pdimm->trp_ps = spd->trp * 250;
pdimm->tras_ps = spd->tras * 1000;
/* Compute timing parameters */
pdimm->trcd_ps = spd->trcd * 250;
pdimm->trp_ps = spd->trp * 250;
pdimm->tras_ps = spd->tras * 1000;
- pdimm->twr_ps = mclk_to_picos(3);
- pdimm->twtr_ps = mclk_to_picos(1);
+ pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
+ pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
pdimm->trrd_ps = spd->trrd * 250;
pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
pdimm->trrd_ps = spd->trrd * 250;
pdimm->tdh_ps
= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
pdimm->tdh_ps
= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
- pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */
+ pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
pdimm->tdqsq_max_ps = spd->tdqsq * 10;
pdimm->tqhs_ps = spd->tqhs * 10;
pdimm->tdqsq_max_ps = spd->tdqsq * 10;
pdimm->tqhs_ps = spd->tqhs * 10;
*
* FIXME: use #define for the retvals
*/
*
* FIXME: use #define for the retvals
*/
-unsigned int
-ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const ddr2_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
& ~(1 << pdimm->caslat_x_minus_1));
/* Compute CAS latencies below that defined by SPD */
- pdimm->caslat_lowest_derated
- = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
+ pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency(
+ get_memory_clk_period_ps(ctrl_num));
/* Compute timing parameters */
pdimm->trcd_ps = spd->trcd * 250;
/* Compute timing parameters */
pdimm->trcd_ps = spd->trcd * 250;
* Writes the results to the dimm_params_t structure pointed by pdimm.
*
*/
* Writes the results to the dimm_params_t structure pointed by pdimm.
*
*/
-unsigned int
-ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const ddr3_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
{
unsigned int retval;
unsigned int mtb_ps;
{
unsigned int retval;
unsigned int mtb_ps;
* Writes the results to the dimm_params_t structure pointed by pdimm.
*
*/
* Writes the results to the dimm_params_t structure pointed by pdimm.
*
*/
-unsigned int
-ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
- dimm_params_t *pdimm,
- unsigned int dimm_number)
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+ const generic_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number)
{
unsigned int retval;
int i;
{
unsigned int retval;
int i;
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(0) >> 20)) << 2;
+ (get_ddr_freq(ctrl_num) >> 20)) << 2;
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
total_gb_size_per_controller >>= 4; /* shift down to gb size */
debug("total %d GB\n", total_gb_size_per_controller);
debug("Need to wait up to %d * 10ms\n", timeout);
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
static unsigned int
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+ const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
{
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
{
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp;
unsigned int caslat_actual;
unsigned int retry = 16;
unsigned int tmp;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
#ifdef CONFIG_SYS_FSL_DDR3
const unsigned int taamax = 20000;
#else
#ifdef CONFIG_SYS_FSL_DDR3
const unsigned int taamax = 20000;
#else
}
#else /* for DDR1 and DDR2 */
static unsigned int
}
#else /* for DDR1 and DDR2 */
static unsigned int
-compute_cas_latency(const dimm_params_t *dimm_params,
+compute_cas_latency(const unsigned int ctrl_num,
+ const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
{
int i;
common_timing_params_t *outpdimm,
unsigned int number_of_dimms)
{
int i;
- const unsigned int mclk_ps = get_memory_clk_period_ps();
+ const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
unsigned int lowest_good_caslat;
unsigned int not_ok;
unsigned int temp1, temp2;
unsigned int lowest_good_caslat;
unsigned int not_ok;
unsigned int temp1, temp2;
* by dimm_params.
*/
unsigned int
* by dimm_params.
*/
unsigned int
-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
+compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
+ const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
const unsigned int number_of_dimms)
{
common_timing_params_t *outpdimm,
const unsigned int number_of_dimms)
{
printf("ERROR: Mix different RDIMM detected!\n");
/* calculate cas latency for all DDR types */
printf("ERROR: Mix different RDIMM detected!\n");
/* calculate cas latency for all DDR types */
- if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms))
+ if (compute_cas_latency(ctrl_num, dimm_params,
+ outpdimm, number_of_dimms))
return 1;
/* Determine if all DIMMs ECC capable. */
return 1;
/* Determine if all DIMMs ECC capable. */
#if defined(CONFIG_SYS_FSL_DDR2)
if ((outpdimm->lowest_common_spd_caslat < 4) &&
#if defined(CONFIG_SYS_FSL_DDR2)
if ((outpdimm->lowest_common_spd_caslat < 4) &&
- (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) {
- additive_latency = picos_to_mclk(trcd_ps) -
+ (picos_to_mclk(ctrl_num, trcd_ps) >
+ outpdimm->lowest_common_spd_caslat)) {
+ additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
outpdimm->lowest_common_spd_caslat;
outpdimm->lowest_common_spd_caslat;
- if (mclk_to_picos(additive_latency) > trcd_ps) {
- additive_latency = picos_to_mclk(trcd_ps);
+ if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
+ additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
debug("setting additive_latency to %u because it was "
" greater than tRCD_ps\n", additive_latency);
}
debug("setting additive_latency to %u because it was "
" greater than tRCD_ps\n", additive_latency);
}
- if (mclk_to_picos(additive_latency) > trcd_ps) {
+ if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
printf("Error: invalid additive latency exceeds tRCD(min).\n");
return 1;
}
printf("Error: invalid additive latency exceeds tRCD(min).\n");
return 1;
}
&(pinfo->spd_installed_dimms[i][j]);
dimm_params_t *pdimm =
&(pinfo->dimm_params[i][j]);
&(pinfo->spd_installed_dimms[i][j]);
dimm_params_t *pdimm =
&(pinfo->dimm_params[i][j]);
- retval = compute_dimm_parameters(spd, pdimm, i);
+ retval = compute_dimm_parameters(
+ i, spd, pdimm, j);
#ifdef CONFIG_SYS_DDR_RAW_TIMING
if (!i && !j && retval) {
printf("SPD error on controller %d! "
#ifdef CONFIG_SYS_DDR_RAW_TIMING
if (!i && !j && retval) {
printf("SPD error on controller %d! "
for (i = first_ctrl; i <= last_ctrl; i++) {
debug("Computing lowest common DIMM"
" parameters for memctl=%u\n", i);
for (i = first_ctrl; i <= last_ctrl; i++) {
debug("Computing lowest common DIMM"
" parameters for memctl=%u\n", i);
- compute_lowest_common_dimm_parameters(
- pinfo->dimm_params[i],
- &timing_params[i],
- CONFIG_DIMM_SLOTS_PER_CTLR);
+ compute_lowest_common_dimm_parameters
+ (i,
+ pinfo->dimm_params[i],
+ &timing_params[i],
+ CONFIG_DIMM_SLOTS_PER_CTLR);
- compute_fsl_memctl_config_regs(
- &pinfo->memctl_opts[i],
- &ddr_reg[i], &timing_params[i],
- pinfo->dimm_params[i],
- dbw_capacity_adjust[i],
- size_only);
+ compute_fsl_memctl_config_regs
+ (i,
+ &pinfo->memctl_opts[i],
+ &ddr_reg[i], &timing_params[i],
+ pinfo->dimm_params[i],
+ dbw_capacity_adjust[i],
+ size_only);
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
- (get_ddr_freq(0) >> 20)) << 1;
+ (get_ddr_freq(ctrl_num) >> 20)) << 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
timeout_save = timeout;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
timeout_save = timeout;
#endif
case 1:
out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
break;
case 1:
out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
break;
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 2
case 2:
out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
break;
case 3:
out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
break;
case 2:
out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
break;
case 3:
out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
break;
}
clrbits_be32(&ddr->sdram_cfg, 0x2);
}
}
clrbits_be32(&ddr->sdram_cfg, 0x2);
}
#endif
/* Global Timing Parameters. */
#endif
/* Global Timing Parameters. */
- debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
+ debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
/* Pick a caslat override. */
popts->cas_latency_override = 0;
/* Pick a caslat override. */
popts->cas_latency_override = 0;
* FIXME: width, was considering looking at pdimm->primary_sdram_width
*/
#if defined(CONFIG_SYS_FSL_DDR1)
* FIXME: width, was considering looking at pdimm->primary_sdram_width
*/
#if defined(CONFIG_SYS_FSL_DDR1)
- popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
+ popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
#elif defined(CONFIG_SYS_FSL_DDR2)
/*
#elif defined(CONFIG_SYS_FSL_DDR2)
/*
if (pdimm[0].n_ranks == 4)
popts->quad_rank_present = 1;
if (pdimm[0].n_ranks == 4)
popts->quad_rank_present = 1;
- ddr_freq = get_ddr_freq(0) / 1000000;
+ ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
if (popts->registered_dimm_en) {
popts->rcw_override = 1;
popts->rcw_1 = 0x000a5a00;
if (popts->registered_dimm_en) {
popts->rcw_override = 1;
popts->rcw_1 = 0x000a5a00;
* propagation, compute a suitably rounded mclk_ps to compute
* a working memory controller configuration.
*/
* propagation, compute a suitably rounded mclk_ps to compute
* a working memory controller configuration.
*/
-unsigned int get_memory_clk_period_ps(void)
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
- unsigned int data_rate = get_ddr_freq(0);
+ unsigned int data_rate = get_ddr_freq(ctrl_num);
unsigned int result;
/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
unsigned int result;
/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
}
/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
}
/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
-unsigned int picos_to_mclk(unsigned int picos)
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
{
unsigned long long clks, clks_rem;
{
unsigned long long clks, clks_rem;
- unsigned long data_rate = get_ddr_freq(0);
+ unsigned long data_rate = get_ddr_freq(ctrl_num);
/* Short circuit for zero picos */
if (!picos)
/* Short circuit for zero picos */
if (!picos)
return (unsigned int) clks;
}
return (unsigned int) clks;
}
-unsigned int mclk_to_picos(unsigned int mclk)
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
- return get_memory_clk_period_ps() * mclk;
+ return get_memory_clk_period_ps(ctrl_num) * mclk;
* to this specific DDR technology.
*/
static __inline__ int
* to this specific DDR technology.
*/
static __inline__ int
-compute_dimm_parameters(const generic_spd_eeprom_t *spd,
+compute_dimm_parameters(const unsigned int ctrl_num,
+ const generic_spd_eeprom_t *spd,
dimm_params_t *pdimm,
unsigned int dimm_number)
{
dimm_params_t *pdimm,
unsigned int dimm_number)
{
- return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
+ return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
unsigned int size_only);
const char *step_to_string(unsigned int step);
unsigned int size_only);
const char *step_to_string(unsigned int step);
-unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+ const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_parameters,
unsigned int dbw_capacity_adjust,
unsigned int size_only);
unsigned int compute_lowest_common_dimm_parameters(
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_parameters,
unsigned int dbw_capacity_adjust,
unsigned int size_only);
unsigned int compute_lowest_common_dimm_parameters(
+ const unsigned int ctrl_num,
const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms);
const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
unsigned int number_of_dimms);
unsigned int ctrl_num);
void check_interleaving_options(fsl_ddr_info_t *pinfo);
unsigned int ctrl_num);
void check_interleaving_options(fsl_ddr_info_t *pinfo);
-unsigned int mclk_to_picos(unsigned int mclk);
-unsigned int get_memory_clk_period_ps(void);
-unsigned int picos_to_mclk(unsigned int picos);
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
void fsl_ddr_set_lawbar(
const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
void fsl_ddr_set_lawbar(
const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
-extern unsigned int ddr_compute_dimm_parameters(
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
const generic_spd_eeprom_t *spd,
dimm_params_t *pdimm,
unsigned int dimm_number);
const generic_spd_eeprom_t *spd,
dimm_params_t *pdimm,
unsigned int dimm_number);