xtensa: fix build for configs without cache options

- make cache-related assembly macros empty if core doesn't have
  corresponding cache type;
- don't initialize cache attributes in instruction/data TLB entries if
  there's no corresponding cache type.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
index 60e1877..e0f9e11 100644 (file)
--- a/arch/xtensa/include/asm/cacheasm.h
+++ b/arch/xtensa/include/asm/cacheasm.h
@@ -73,7 +73,9 @@
 
        .macro  ___unlock_dcache_all ar at
 
 
        .macro  ___unlock_dcache_all ar at
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
        __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .endm
 


@@ -90,30 +92,38 @@
 
        .macro  ___flush_invalidate_dcache_all ar at
 
 
        .macro  ___flush_invalidate_dcache_all ar at
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
        __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___flush_dcache_all ar at
 
 
        .endm
 
 
        .macro  ___flush_dcache_all ar at
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
        __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___invalidate_dcache_all ar at
 
 
        .endm
 
 
        .macro  ___invalidate_dcache_all ar at
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
                         XCHAL_DCACHE_LINEWIDTH
        __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
                         XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___invalidate_icache_all ar at
 
 
        .endm
 
 
        .macro  ___invalidate_icache_all ar at
 

+#if XCHAL_ICACHE_SIZE

        __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
                         XCHAL_ICACHE_LINEWIDTH
        __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
                         XCHAL_ICACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .endm
 


@@ -121,28 +131,36 @@
 
        .macro  ___flush_invalidate_dcache_range ar as at
 
 
        .macro  ___flush_invalidate_dcache_range ar as at
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
        __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___flush_dcache_range ar as at
 
 
        .endm
 
 
        .macro  ___flush_dcache_range ar as at
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
        __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___invalidate_dcache_range ar as at
 
 
        .endm
 
 
        .macro  ___invalidate_dcache_range ar as at
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
        __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___invalidate_icache_range ar as at
 
 
        .endm
 
 
        .macro  ___invalidate_icache_range ar as at
 

+#if XCHAL_ICACHE_SIZE

        __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
        __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .endm
 


@@ -150,27 +168,35 @@
 
        .macro  ___flush_invalidate_dcache_page ar as
 
 
        .macro  ___flush_invalidate_dcache_page ar as
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
        __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro ___flush_dcache_page ar as
 
 
        .endm
 
 
        .macro ___flush_dcache_page ar as
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
        __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___invalidate_dcache_page ar as
 
 
        .endm
 
 
        .macro  ___invalidate_dcache_page ar as
 

+#if XCHAL_DCACHE_SIZE

        __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
        __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH

+#endif

 
        .endm
 
 
        .macro  ___invalidate_icache_page ar as
 
 
        .endm
 
 
        .macro  ___invalidate_icache_page ar as
 

+#if XCHAL_ICACHE_SIZE

        __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
        __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH

+#endif

 
        .endm
 
        .endm

diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index e256f22..7a1e075 100644 (file)
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -161,7 +161,8 @@
 #endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
          XCHAL_HAVE_SPANNING_WAY */
 
 #endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
          XCHAL_HAVE_SPANNING_WAY */
 

-#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
+#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS && \
+               (XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE)

        /* Enable data and instruction cache in the DEFAULT_MEMORY region
         * if the processor has DTLB and ITLB.
         */
        /* Enable data and instruction cache in the DEFAULT_MEMORY region
         * if the processor has DTLB and ITLB.
         */


@@ -175,14 +176,18 @@
 1:
        sub     a9, a9, a8
 2:
 1:
        sub     a9, a9, a8
 2:

+#if XCHAL_DCACHE_SIZE

        rdtlb1  a3, a5
        rdtlb1  a3, a5

-       ritlb1  a4, a5

        and     a3, a3, a6
        and     a3, a3, a6

-       and     a4, a4, a6

        or      a3, a3, a7
        or      a3, a3, a7

-       or      a4, a4, a7

        wdtlb   a3, a5
        wdtlb   a3, a5

+#endif
+#if XCHAL_ICACHE_SIZE
+       ritlb1  a4, a5
+       and     a4, a4, a6
+       or      a4, a4, a7

        witlb   a4, a5
        witlb   a4, a5

+#endif

        add     a5, a5, a8
        bltu    a8, a9, 1b
 
        add     a5, a5, a8
        bltu    a8, a9, 1b