static int __maybe_unused starfive_pinctrl_suspend(struct device *dev)
{
struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
+ u8 i;
+
+ for (i = 0 ; i < SYS_IRQ_REG_SUSPENDED_NUM ; i++)
+ pctl->sys_irq_reg_suspended[i] =
+ readl_relaxed(pctl->padctl_base + GPIO_EN + OFFSET_PER_REG * i);
+
+ for (i = 0 ; i < AON_IRQ_REG_SUSPENDED_NUM ; i++)
+ pctl->aon_irq_reg_suspended[i] =
+ readl_relaxed(pctl->padctl_base + AON_GPIO_EN_REG + OFFSET_PER_REG * i);
return pinctrl_force_sleep(pctl->pctl_dev);
}
static int __maybe_unused starfive_pinctrl_resume(struct device *dev)
{
struct starfive_pinctrl *pctl = dev_get_drvdata(dev);
+ u8 i;
+
+ for (i = 0 ; i < SYS_IRQ_REG_SUSPENDED_NUM ; i++)
+ writel_relaxed(pctl->sys_irq_reg_suspended[i],
+ pctl->padctl_base + GPIO_EN + OFFSET_PER_REG * i);
+
+ for (i = 0 ; i < AON_IRQ_REG_SUSPENDED_NUM ; i++)
+ writel_relaxed(pctl->aon_irq_reg_suspended[i],
+ pctl->padctl_base + AON_GPIO_EN_REG + OFFSET_PER_REG * i);
return pinctrl_force_default(pctl->pctl_dev);
}
#define STARFIVE_USE_SCU BIT(0)
+#define SYS_IRQ_REG_SUSPENDED_NUM 11
+#define AON_IRQ_REG_SUSPENDED_NUM 6
+
struct platform_device;
extern const struct pinmux_ops starfive_pmx_ops;
struct pinctrl_gpio_range gpios;
unsigned long enabled;
unsigned int trigger[MAX_GPIO];
+
+ u32 sys_irq_reg_suspended[SYS_IRQ_REG_SUSPENDED_NUM];
+ u32 aon_irq_reg_suspended[AON_IRQ_REG_SUSPENDED_NUM];
};
struct starfive_pinctrl_soc_info {