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ASoC: Samsung: reset the BUS clock divider ratio from 2 to 10 92/20692/3
authorChen Zhen <zhen1.chen@samsung.com>
Mon, 12 May 2014 05:51:00 +0000 (13:51 +0800)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Thu, 15 May 2014 10:16:02 +0000 (03:16 -0700)
commit93eb828c65f40271478934223b8cfe29e62dd562
tree6aafdfa1aa595ef3f79993bce5d6828a84e4ebdatree | snapshot
parent70b7010db5f972d5f4ef689fc530e650d693202ecommit | diff
ASoC: Samsung: reset the BUS clock divider ratio from 2 to 10

when codec work at master mode, the CDCLK was used to MCLK for codec,
but previous CDCLK was too big for max98090,so change its divider
ratio from 2 to 10,and now the CDCLK is 19.2MHz.

Change-Id: I6246cdc85e1b33b0c2bc2128135b27bbc7c00ccb
Signed-off-by: Chen Zhen <zhen1.chen@samsung.com>
sound/soc/samsung/i2s.c diff | blob | history
Domain: System / Kernel;