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(parent: 28d7d61) | patch
mmc: meson_gx_mmc: control ddr_mode bit 77/247377/1
authorJaehoon Chung <jh80.chung@samsung.com>
Tue, 10 Nov 2020 07:44:53 +0000 (16:44 +0900)
committerJaehoon Chung <jh80.chung@samsung.com>
Tue, 10 Nov 2020 08:04:14 +0000 (17:04 +0900)
commitcfd6d8938d340df8779ba9edc01122324461a5c8
tree646f34801c0d1ec1a4452337556db92a83d73febtree | snapshot
parent28d7d61330770c4eaae908bbe010bb548fcaec46commit | diff
mmc: meson_gx_mmc: control ddr_mode bit

EMMC_CFG register has a cfg_ddr bit(BIT[2]).
It needs to set when mmc is running to ddr mode.
Otherwise, its bit should be cleared.
CFG_DDR[2] - 1: DDR mode, 0: SDR mode

Change-Id: I5b1ddc6492e9c0d90e974fa31b13eacdee6e38e3
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
arch/arm/include/asm/arch-meson/sd_emmc.h diff | blob | history
drivers/mmc/meson_gx_mmc.c diff | blob | history
Domain: System / Kernel;