[Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops
authorPierre-vh <pierre.vanhoutryve@arm.com>
Tue, 7 Apr 2020 14:09:56 +0000 (15:09 +0100)
committerPierre-vh <pierre.vanhoutryve@arm.com>
Tue, 5 May 2020 09:03:02 +0000 (10:03 +0100)
commitffdda495f79a3147c4b351b323235ec429cc4f7d
tree28a786d44546846671e541f2713a5a19d9a63be9
parent48aebfc908ba7b9372aaa478a9c200789491096e
[Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops

This patch adds an implementation of PerformVSELECTCombine in the
ARM DAG Combiner that transforms vselect(not(cond), lhs, rhs) into
vselect(cond, rhs, lhs).

Normally, this should be done by the target-independent DAG Combiner,
but it doesn't handle the kind of constants that we generate, so we
have to reimplement it here.

Differential Revision: https://reviews.llvm.org/D77712
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb2/mve-pred-or.ll
llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll