drm/msm/dsi: Populate the 10nm PHY funcs
authorArchit Taneja <architt@codeaurora.org>
Wed, 17 Jan 2018 06:05:27 +0000 (11:35 +0530)
committerRob Clark <robdclark@gmail.com>
Tue, 20 Feb 2018 15:41:21 +0000 (10:41 -0500)
commitff73ff19406098f71ec7628b951e0765f1df8128
tree453848b889f930350430d98cb518abc0d42ae796
parent28e4309ab9c2bade2a93bd3b4c583be5ec440b84
drm/msm/dsi: Populate the 10nm PHY funcs

Populate the PHY ops with the downstream driver as reference.

There are a couple of TODOs which need to be resolved:
- The PHY timings are all hardcoded for now. This needs to be replaced
  with automatic calculations once we get/understand them.
- There are some lane configuration registers which use a new
  representation between physical and logical lane mappings. For now,
  we've hardcoced them to follow the default mapping (i.e
  logical 0 -> phy 0, logical 1 -> phy 1 etc).

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c