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ASoC: mediatek: mt8195: enable apll tuner
authorTrevor Wu <trevor.wu@mediatek.com>
Mon, 21 Feb 2022 05:57:16 +0000 (13:57 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 21 Feb 2022 13:24:56 +0000 (13:24 +0000)
commitff5a90173d981934e1134d28af3625acaab01d80
tree9087952e0f1340f62871bec4d8edfb59512ac601tree | snapshot
parentb9afe038b1fba24e815000606d5877de97f9f154commit | diff
ASoC: mediatek: mt8195: enable apll tuner

Normally, the clock source of audio module is either 26M or APLL1/APLL2,
but APLL1/APLL2 are not the multiple of 26M.

In the patch, APLL1 and APLL2 tuners are enabled to handle sample rate
mismatch when the data path crosses two different clock domains.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Link: https://lore.kernel.org/r/20220221055716.18580-1-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/mediatek/mt8195/mt8195-afe-clk.c diff | blob | history
sound/soc/mediatek/mt8195/mt8195-afe-clk.h diff | blob | history
sound/soc/mediatek/mt8195/mt8195-afe-pcm.c diff | blob | history
Domain: System / Kernel;