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(parent: d742ea6) | patch
dt-bindings: net: tsnep: Allow dma-coherent
authorGerhard Engleder <gerhard@engleder-embedded.com>
Tue, 27 Sep 2022 19:58:37 +0000 (21:58 +0200)
committerDavid S. Miller <davem@davemloft.net>
Fri, 30 Sep 2022 10:31:34 +0000 (11:31 +0100)
commitff46c610abd62a3dc120dc05ad726b2a47d347ea
tree3601476e89eae72fb67be46741d02dd687e47944tree | snapshot
parentd742ea6b8e85f7b0d484bc23392d607b50667da6commit | diff
dt-bindings: net: tsnep: Allow dma-coherent

Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.

Add "dma-coherent" property to allow the configuration of cache coherent
DMA.

Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Documentation/devicetree/bindings/net/engleder,tsnep.yaml diff | blob | history
Domain: System / Kernel;