intel/compiler/xe2: Handle new URB write messages
authorIan Romanick <ian.d.romanick@intel.com>
Wed, 20 Jul 2022 17:21:21 +0000 (10:21 -0700)
committerMarge Bot <emma+marge@anholt.net>
Wed, 27 Sep 2023 23:57:25 +0000 (23:57 +0000)
commitfeec9166cdb2d562e741a2775b3fa87fc0876707
treea4b38fbdec34cbcbd906886a7be37fa5b9bae3e7
parentfa53a7d2413f1fc26af7c3091ef11db292e3dd97
intel/compiler/xe2: Handle new URB write messages

Rework:
 * idr v1: Fix compilation error.
 * idr v2: Add support for per-channel offsets.
 * idr v3: get_lowered_simd_width is 16 on Xe2+.
 * idr v4: Add disassembly support.  Add validation support.
 * Sqaushed in changes Marcin Ĺšlusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
src/intel/compiler/brw_disasm.c
src/intel/compiler/brw_eu_validate.c
src/intel/compiler/brw_fs.cpp
src/intel/compiler/brw_lower_logical_sends.cpp