RISC-V: simplify register width check in ISA string parsing
authorConor Dooley <conor.dooley@microchip.com>
Wed, 7 Jun 2023 20:28:25 +0000 (21:28 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 21 Jun 2023 14:45:13 +0000 (07:45 -0700)
commitfed14be476f075a523fd4addfee07cb2f8dc1971
treec8beb705c7d091f9aca1525e4c1f4cdfd474148d
parent748462b59f901557377b2c33ea9808ff2000e141
RISC-V: simplify register width check in ISA string parsing

Saving off the `isa` pointer to a temp variable, followed by checking if
it has been incremented is a bit of an odd pattern. Perhaps it was done
to avoid a funky looking if statement mixed with the ifdeffery.

Now that we use IS_ENABLED() here just return from the parser as soon as
we detect a mismatch between the string and the currently running
kernel.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230607-splatter-bacterium-a75bb9f0d0b7@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/kernel/cpufeature.c