projects / platform / kernel / linux-starfive.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 1e9fc6c) | patch
arm64: dts: ti: k3-am625: Correct L2 cache size to 512KB
authorVignesh Raghavendra <vigneshr@ti.com>
Mon, 20 Mar 2023 04:49:34 +0000 (10:19 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 11 May 2023 14:03:10 +0000 (23:03 +0900)
commitfe9dc0a2643e6fa1866f8056095a8466381d73dd
tree49862485357bce789e8307551fe2caf0e6458366tree | snapshot
parent1e9fc6c473210138eff3425a6136f0a9bf4eb0aecommit | diff
arm64: dts: ti: k3-am625: Correct L2 cache size to 512KB

[ Upstream commit 6974371cab1c488a53960945cb139b20ebb5f16b ]

Per AM62x SoC datasheet[0] L2 cache is 512KB.

[0] https://www.ti.com/lit/gpn/am625 Page 1.

Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/ti/k3-am625.dtsi diff | blob | history
Domain: System / Kernel;