drm/i915: Get proper min cdclk if vDSC enabled
authorLee Shawn C <shawn.c.lee@intel.com>
Wed, 8 Sep 2021 11:56:05 +0000 (19:56 +0800)
committerVandita Kulkarni <vandita.kulkarni@intel.com>
Wed, 8 Sep 2021 14:04:39 +0000 (19:34 +0530)
commitfe01883fdcefd09c7ceb91874c2f74ae074163d6
treefc3903591abb5731f1a3dcfdbbf495c21b83aade
parent5ebd50d3948ee596db02399a09b4561ed82aee57
drm/i915: Get proper min cdclk if vDSC enabled

VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.

v2:
- Check for dsc enable and slice count ==1 then allow to
  double confirm min cdclk value.

Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Cc: William Tseng <william.tseng@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210908115607.9633-4-shawn.c.lee@intel.com
drivers/gpu/drm/i915/display/intel_cdclk.c