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[DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTM...
authorCraig Topper <craig.topper@intel.com>
Sun, 9 Aug 2020 05:09:21 +0000 (22:09 -0700)
committerCraig Topper <craig.topper@intel.com>
Sun, 9 Aug 2020 05:27:16 +0000 (22:27 -0700)
commitfdfdee98ac81dc7554bb2d7f5e99614e0086b4f0
tree98b91c104fc00020e0520542d9a1b9c00e41a768tree | snapshot
parent95e61ed85c1abb7dab20ab665d6204ea66f5bf1fcommit | diff
[DAGCombiner] Teach SimplifySetCC SETUGE X, SINTMIN -> SETLT X, 0 and SETULE X, SINTMAX  -> SETGT X, -1.

These aren't the canonical forms we'd get from InstCombine, but
we do have X86 tests for them. Recognizing them is pretty cheap.

While there make use of APInt:isSignedMinValue/isSignedMaxValue
instead of creating a new APInt to compare with. Also use
SelectionDAG::getAllOnesConstant helper to hide the all ones
APInt creation.
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/vector-compare-simplify.ll diff | blob | history
Domain: System / Toolchain;