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(parent: 9e071aa) | patch
x86: Add TSX Force Abort CPUID/MSR
authorPeter Zijlstra (Intel) <peterz@infradead.org>
Tue, 5 Mar 2019 21:23:17 +0000 (22:23 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 13 Mar 2019 21:02:41 +0000 (14:02 -0700)
commitfdd820949a745930738720c518df38e5dc99b3c2
tree0d0f7bf4057d5dddb729b8b519974bf8608148catree | snapshot
parent9e071aa6c28c6d8eda7e2ee3663abf3d561a66a8commit | diff
x86: Add TSX Force Abort CPUID/MSR

commit 52f64909409c17adf54fcf5f9751e0544ca3a6b4 upstream

Skylake systems will receive a microcode update to address a TSX
errata. This microcode will (by default) clobber PMC3 when TSX
instructions are (speculatively or not) executed.

It also provides an MSR to cause all TSX transaction to abort and
preserve PMC3.

Add the CPUID enumeration and MSR definition.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/x86/include/asm/cpufeatures.h diff | blob | history
arch/x86/include/asm/msr-index.h diff | blob | history
Domain: System / Kernel;