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(parent: 7dd4377) | patch
[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
authorAlex Bradbury <asb@lowrisc.org>
Thu, 26 Apr 2018 15:34:27 +0000 (15:34 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Thu, 26 Apr 2018 15:34:27 +0000 (15:34 +0000)
commitfda6037e98694b74488614a099b06abffa7f0766
tree136702922422e1830d8d4a185e62dd243fbc7259tree | snapshot
parent7dd437710e821ef76717611f6f23f849d2cf9ca8commit | diff
[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot

This causes some slight shuffling but no meaningful codegen differences on the
corpus I used for testing, but it has a larger impact when combined with e.g.
rematerialisation. Regardless, it makes sense to report as accurate
target-specific information as possible.

llvm-svn: 330949
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.h diff | blob | history
Domain: System / Toolchain;