projects / platform / upstream / dotnet / runtime.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: f4df16b) | patch
Implement LeadingSignCount,LeadingZeroCount,PopCount (dotnet/coreclr#27568)
authorEgor Chesakov <Egor.Chesakov@microsoft.com>
Sun, 3 Nov 2019 20:42:55 +0000 (12:42 -0800)
committerGitHub <noreply@github.com>
Sun, 3 Nov 2019 20:42:55 +0000 (12:42 -0800)
commitfd5a1f6329c776ef3bc66400ca3065c74871ac97
tree168544ba7a8ea9a78ab000700d278cd9b855b954tree | snapshot
parentf4df16b68526df46f4b437c48d3165ebef9a18cacommit | diff
Implement LeadingSignCount,LeadingZeroCount,PopCount (dotnet/coreclr#27568)

Commit migrated from https://github.com/dotnet/coreclr/commit/a76dda01562ec04be3ef1847f786e0a6a969c2b6
37 files changed:
src/coreclr/src/jit/hwintrinsiclistarm64.h diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_r.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_ro.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingSignCount.Vector128.Int16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingSignCount.Vector128.Int32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingSignCount.Vector128.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingSignCount.Vector64.Int16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingSignCount.Vector64.Int32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingSignCount.Vector64.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector128.Byte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector128.Int16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector128.Int32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector128.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector128.UInt16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector128.UInt32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector64.Byte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector64.Int16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector64.Int32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector64.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector64.UInt16.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/LeadingZeroCount.Vector64.UInt32.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/PopCount.Vector128.Byte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/PopCount.Vector128.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/PopCount.Vector64.Byte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/PopCount.Vector64.SByte.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/Program.AdvSimd.cs diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/Aes_r.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Aes/Aes_ro.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/ArmBase.Arm64_r.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase.Arm64/ArmBase.Arm64_ro.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase/ArmBase_r.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/ArmBase/ArmBase_ro.csproj diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/GenerateTests.csx diff | blob | history
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs [new file with mode: 0644] blob
src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/Shared/Helpers.tt [new file with mode: 0644] blob
Domain: Dotnet / Core;