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(parent: a29383d) | patch
imx8ulp_evk: Update the DDR timing
authorJacky Bai <ping.bai@nxp.com>
Tue, 31 Jan 2023 08:42:30 +0000 (16:42 +0800)
committerStefano Babic <sbabic@denx.de>
Wed, 29 Mar 2023 18:15:42 +0000 (20:15 +0200)
commitfd3cb1d977292be9f0ca803f869108c222bbea36
treeb5e35ae2171efb654e12445427f3aa3381c89fc8tree | snapshot
parenta29383da7231774808c6034ca68b0231520058a4commit | diff
imx8ulp_evk: Update the DDR timing

Update the dram timing to support PLL bypass mode
for F1.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
board/freescale/imx8ulp_evk/lpddr4_timing.c diff | blob | history
Domain: System / Kernel;