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(parent: f59b016) | patch
clk: tegra: Fix typos around clearing PLLE bits during enable
authorRhyland Klein <rklein@nvidia.com>
Thu, 14 Jan 2016 19:24:37 +0000 (14:24 -0500)
committerThierry Reding <treding@nvidia.com>
Tue, 2 Feb 2016 14:49:26 +0000 (15:49 +0100)
commitfd2963b071c1346572285a274a6ae8f26a970c4d
treebdc7652551379221c049a13f595ec97db81adff6tree | snapshot
parentf59b0168d3f3257f9bf0734563290acc3c9d972bcommit | diff
clk: tegra: Fix typos around clearing PLLE bits during enable

While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
them. This patch fixes both places where we incorrectly set instead of
cleared those bits.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c diff | blob | history
Domain: System / Kernel;