[SVE][CodeGen] Lower scalable fp_extend & fp_round operations
authorKerry McLaughlin <kerry.mclaughlin@arm.com>
Thu, 1 Oct 2020 10:06:55 +0000 (11:06 +0100)
committerKerry McLaughlin <kerry.mclaughlin@arm.com>
Thu, 1 Oct 2020 11:17:37 +0000 (12:17 +0100)
commitfcf70e1e3b1d57d5fde6b99d0188d1b1774429af
tree62a7d8b1ee9f85f7330eda4f1c57fbab064bd02b
parenta81b938b6dee0e1ed4dd44e7d59325d0aa4774cc
[SVE][CodeGen] Lower scalable fp_extend & fp_round operations

This patch adds FP_EXTEND_MERGE_PASSTHRU & FP_ROUND_MERGE_PASSTHRU
ISD nodes, used to lower scalable vector fp_extend/fp_round operations.
fp_round has an additional argument, the 'trunc' flag, which is an integer of zero or one.

This also fixes a warning introduced by the new tests added to sve-split-fcvt.ll,
resulting from an implicit TypeSize -> uint64_t cast in SplitVecOp_FP_ROUND.

Reviewed By: sdesmalen, paulwalker-arm

Differential Revision: https://reviews.llvm.org/D88321
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve-fcvt.ll
llvm/test/CodeGen/AArch64/sve-split-fcvt.ll