[ARM] MVE VMULL patterns
authorDavid Green <david.green@arm.com>
Wed, 1 Apr 2020 12:58:42 +0000 (13:58 +0100)
committerDavid Green <david.green@arm.com>
Thu, 2 Apr 2020 09:57:40 +0000 (10:57 +0100)
commitfbd53ffc3ad97bf39cc1420ac160f402f6a0c935
tree6e3aa624447001980d005212f0f8cd38d389c0f4
parentc697dd9ffdb14f08766c738eb28c377ee964937f
[ARM] MVE VMULL patterns

This adds MVE vmull patterns, which are conceptually the same as
mul(vmovl, vmovl), and so the tablegen patterns follow the same
structure.

For i8 and i16 this is simple enough, but in the i32 version the
multiply (in 64bits) is illegal, meaning we need to catch the pattern
earlier in a dag fold. Because bitcasts are involved in the zext
versions and the patterns are a little different in little and big
endian. I have only added little endian support in this patch.

Differential Revision: https://reviews.llvm.org/D76740
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/lib/Target/ARM/ARMInstrNEON.td
llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll
llvm/test/CodeGen/Thumb2/mve-vmull.ll