perf/x86/intel: Add 1G DTLB load/store miss support for SKL
authorKan Liang <Kan.liang@intel.com>
Mon, 19 Jun 2017 14:26:09 +0000 (07:26 -0700)
committerIngo Molnar <mingo@kernel.org>
Thu, 22 Jun 2017 09:07:08 +0000 (11:07 +0200)
commitfb3a5055cd7098f8d1dd0cd38d7172211113255f
tree44d585383e1e2c9f6ca9eb74bed8e24bcb08d688
parent8a1898db51a3390241cd5fae267dc8aaa9db0f8b
perf/x86/intel: Add 1G DTLB load/store miss support for SKL

Current DTLB load/store miss events (0x608/0x649) only counts 4K,2M and
4M page size.
Need to extend the events to support any page size (4K/2M/4M/1G).

The complete DTLB load/store miss events are:

  DTLB_LOAD_MISSES.WALK_COMPLETED 0xe08
  DTLB_STORE_MISSES.WALK_COMPLETED 0xe49

Signed-off-by: Kan Liang <Kan.liang@intel.com>
Cc: <stable@vger.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/20170619142609.11058-1-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/events/intel/core.c