[AArch64] Add the Ampere1A core
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Tue, 24 Jan 2023 21:28:22 +0000 (22:28 +0100)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Tue, 24 Jan 2023 21:36:39 +0000 (22:36 +0100)
commitfb0af89193a9ea0f92eaffb454341987f897f0c7
tree976c146162b706af072827818d47d00d4fc9ead7
parentd8ce50e3c25f667a10750d1129a1b8a060d43492
[AArch64] Add the Ampere1A core

The Ampere1A core improves on the Ampere1 with key differences being:
 * memory tagging is supported
 * SM3/SM4 are supported
 * adds a new fusion pair for (A+B+1 and A-B-1)
   (added in a later commit)

Depends on D142395

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D142396
14 files changed:
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/TargetParser/Host.cpp
llvm/test/CodeGen/AArch64/cpus.ll
llvm/test/CodeGen/AArch64/neon-dot-product.ll
llvm/test/CodeGen/AArch64/remat.ll
llvm/test/MC/AArch64/armv8.2a-dotprod.s
llvm/test/MC/AArch64/armv8.3a-rcpc.s
llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
llvm/unittests/TargetParser/Host.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp