[X86] Add VEXTRB/W/D/Q to Zen scheduler model.
authorCraig Topper <craig.topper@intel.com>
Fri, 23 Mar 2018 06:41:36 +0000 (06:41 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 23 Mar 2018 06:41:36 +0000 (06:41 +0000)
commitfae4173b475a16aa12076fb752a7a905a560a2f3
tree16116e0b4b92d3d70ee86a6a7470d01339d468e2
parent6ef55d1887d05476c9e881256e97e2577bee20bf
[X86] Add VEXTRB/W/D/Q to Zen scheduler model.

The SSE versions were present, but not the VEX version.

llvm-svn: 328290
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/test/CodeGen/X86/sse-schedule.ll
llvm/test/CodeGen/X86/sse2-schedule.ll
llvm/test/CodeGen/X86/sse41-schedule.ll