projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 77b46fb) | patch
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
authorPaolo Savini <paolo.savini@embecosm.com>
Thu, 9 Apr 2020 16:51:10 +0000 (17:51 +0100)
committerSimon Cook <simon.cook@embecosm.com>
Thu, 9 Apr 2020 17:04:22 +0000 (18:04 +0100)
commitfae40bd5a1d4d0ef5f60d5a441757d39a06ce077
tree5c86e7d20d867920fca39ec382bb5af65605f967tree | snapshot
parent77b46fb326b595e984a540e676187d4d01750e60commit | diff
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

This adds the instruction encoding and mnenomics for the proposed
RISC-V Bit Manipulation extension (version 0.92). It is implemented with
each category of instruction as its own target feature, with the 'b'
extension feature enabling all options. Since this extension is not yet
ratified, all target features are prefixed with 'experimental-' to note
their status.

Differential Revision: https://reviews.llvm.org/D65649
52 files changed:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp diff | blob | history
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoB.td [new file with mode: 0644] blob
llvm/lib/Target/RISCV/RISCVSubtarget.h diff | blob | history
llvm/test/MC/RISCV/compress-rv32b.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/compress-rv64b.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32b-aliases-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbb-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbb-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbbp-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbbp-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbc-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbc-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbe-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbe-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbf-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbf-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbp-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbp-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbproposedc-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbproposedc-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbr-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbr-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbs-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbs-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbt-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv32zbt-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64b-aliases-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbb-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbb-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbbp-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbbp-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbc-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbc-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbe-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbe-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbf-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbf-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbm-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbm-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbp-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbp-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbproposedc-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbproposedc-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbr-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbr-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbs-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbs-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbt-invalid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rv64zbt-valid.s [new file with mode: 0644] blob
Domain: System / Toolchain;