usb: dwc3: workaround: U1/U2 -> U0 transiton
authorFelipe Balbi <balbi@ti.com>
Fri, 14 Oct 2011 10:00:30 +0000 (13:00 +0300)
committerFelipe Balbi <balbi@ti.com>
Mon, 12 Dec 2011 09:48:34 +0000 (11:48 +0200)
commitfae2b904aa85beecd0950026de28921ae65fb3da
treeb8f5a84150854fedb435b4c90948b2ae10ef1178
parentd39ee7be2aaf0a53d7b5f43c13571bac95f7cc0c
usb: dwc3: workaround: U1/U2 -> U0 transiton

RTL revisions <1.83a have an issue where, depending
on the link partner, the USB link might do multiple
entry/exit of low power states before a transfer
takes place causing degraded throughput.

The suggested workaround is to clear bits
12:9 of DCTL register if we see a transition
from U1|U2 to U0 and only re-enable that on
a transfer complete IRQ and we have no pending
transfers on any of the enabled endpoints.

Signed-off-by: Felipe Balbi <balbi@ti.com>
drivers/usb/dwc3/core.h
drivers/usb/dwc3/gadget.c