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(parent: f170ff6) | patch
Added more features to the instruction scheduler to support both pre-register
authorBenjamin Segovia <benjamin.segovia@intel.com>
Wed, 7 Nov 2012 01:42:51 +0000 (17:42 -0800)
committerBenjamin Segovia <benjamin.segovia@intel.com>
Wed, 7 Nov 2012 01:42:51 +0000 (17:42 -0800)
commitfacc3bc4f58ea04b539588b59733026024055885
treeb45c4a09f3dd7aa47d4091829ca288404644e4e1tree | snapshot
parentf170ff61100affbdef99e070907c2e2142bcc784commit | diff
Added more features to the instruction scheduler to support both pre-register
allocation and post-register allocation scheduling
Well, we really need to implement something really good for the pre-reg
allocation scheduling to avoid spilling (which is not supported anyway today)
backend/src/backend/gen_context.cpp diff | blob | history
backend/src/backend/gen_context.hpp diff | blob | history
backend/src/backend/gen_insn_scheduling.cpp diff | blob | history
backend/src/backend/gen_insn_scheduling.hpp diff | blob | history
backend/src/backend/gen_insn_selection.cpp diff | blob | history
backend/src/backend/gen_program.cpp diff | blob | history
backend/src/backend/gen_reg_allocation.cpp diff | blob | history
backend/src/ocl_stdlib.h diff | blob | history
backend/src/ocl_stdlib_str.cpp diff | blob | history
utests/compiler_shader_toy.cpp diff | blob | history
Domain: SCM / Uncategorized;