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(parent: cabdf83) | patch
usb: dwc3: Add SoftReset PHY synchonization delay
authorThinh Nguyen <Thinh.Nguyen@synopsys.com>
Fri, 16 Mar 2018 22:33:48 +0000 (15:33 -0700)
committerFelipe Balbi <felipe.balbi@linux.intel.com>
Thu, 22 Mar 2018 08:48:46 +0000 (10:48 +0200)
commitfab3833338779e1e668bd58d1f76d601657304b8
treea7071ba2b0f8b27bfadc3600040378fdf2b5bd65tree | snapshot
parentcabdf83dadfb3d83eec31e0f0638a92dbd716435commit | diff
usb: dwc3: Add SoftReset PHY synchonization delay

From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
drivers/usb/dwc3/core.c diff | blob | history
Domain: System / Kernel;