sim: trace: add a basic cpu register class
authorMike Frysinger <vapier@gentoo.org>
Wed, 24 Jun 2015 13:52:21 +0000 (19:37 +0545)
committerMike Frysinger <vapier@gentoo.org>
Wed, 24 Jun 2015 14:40:17 +0000 (10:40 -0400)
commitfa8f87e53b68881c5e3aab296b517203407c4378
tree6eb1f8996ae765cd81589f6c8e8f318ee92a673b
parentcf304b56ca48631836bdc4035134b5b5ec3b9d49
sim: trace: add a basic cpu register class

The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu).  Add
a proper register class for these and for other ports.
sim/bfin/ChangeLog
sim/bfin/interp.c
sim/bfin/sim-main.h
sim/common/ChangeLog
sim/common/sim-trace.c
sim/common/sim-trace.h
sim/msp430/ChangeLog
sim/msp430/msp430-sim.c