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[RISCV] Implement floating point assembler pseudo instructions
authorAlex Bradbury <asb@lowrisc.org>
Wed, 13 Dec 2017 11:37:19 +0000 (11:37 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Wed, 13 Dec 2017 11:37:19 +0000 (11:37 +0000)
commitfa7e4ec8373d031b85f9ae734ab01fb862b2d6ba
tree83338e67dc06bab83b5c0ebe678f8d59c427ce63tree | snapshot
parente0edb66475dd3dd4adf55cb00cdd06e596b199efcommit | diff
[RISCV] Implement floating point assembler pseudo instructions

Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon D40902.

Differential Revision: https://reviews.llvm.org/D41071

Patch by Mario Werner.

llvm-svn: 320569
llvm/lib/Target/RISCV/RISCVInstrInfoD.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoF.td diff | blob | history
llvm/test/MC/RISCV/rvd-aliases-valid.s [new file with mode: 0644] blob
llvm/test/MC/RISCV/rvf-aliases-valid.s [new file with mode: 0644] blob
Domain: System / Toolchain;