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(parent: c2ff081) | patch
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Wed, 9 Sep 2020 13:13:28 +0000 (22:13 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 10 Sep 2020 14:58:13 +0000 (16:58 +0200)
commitfa2d185f7518423ffcdba617ad09ff77ac51f198
tree46996de71e38acfd680f67a9b4fb507a9c1b1e19tree | snapshot
parentc2ff0810934a925c9e6d96d7c400dee9bef8808ecommit | diff
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions

Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V3U (R8A779A0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1599657211-17504-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r8a779a0-cpg-mssr.h [new file with mode: 0644] blob
Domain: System / Kernel;