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(parent: 168fbf7) | patch
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
authorSwapnil Jakhade <sjakhade@cadence.com>
Fri, 28 Jan 2022 08:11:49 +0000 (13:41 +0530)
committerTom Rini <trini@konsulko.com>
Tue, 8 Feb 2022 16:00:04 +0000 (11:00 -0500)
commitfa294b274ba0005fbee5ddd6da15aee5483073ae
treebd865653bcf44e61975ebc2c2ee823ce0e500046tree | snapshot
parent168fbf79db2aa2b8f123fc3a060f38789e113aa2commit | diff
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration

Add register sequences for PCIe + QSGMII PHY multilink configuration.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | history
Domain: System / Kernel;