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[DAGCombiner][RISCV] Improve computeKnownBits for (smax X, C) where C is non-negative.
authorCraig Topper <craig.topper@sifive.com>
Thu, 2 Jun 2022 19:25:40 +0000 (12:25 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 2 Jun 2022 19:34:24 +0000 (12:34 -0700)
commitfa20bf1636a8f3cbcbabcf6cdc21a817935201f7
tree20d8193f7fd970fb8deab310f11ec0d3df999025tree | snapshot
parent4be36dc77fc96766988344b54f6ab5aade86e1c6commit | diff
[DAGCombiner][RISCV] Improve computeKnownBits for (smax X, C) where C is non-negative.

If C is non-negative, the result of the smax must also be
non-negative, so all sign bits of the result are 0.

This allows DAGCombiner to remove a zext_inreg in the modified test.
This zext_inreg started as a sext that became zext before type
legalization then was promoted to a zext_inreg.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126896
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/min-max.ll diff | blob | history
Domain: System / Toolchain;