clk: socfpga: Add initial Arria10 clock driver
authorMarek Vasut <marex@denx.de>
Tue, 31 Jul 2018 15:58:07 +0000 (17:58 +0200)
committerMarek Vasut <marex@denx.de>
Mon, 13 Aug 2018 20:35:42 +0000 (22:35 +0200)
commitf9f016adcdc686bf3c50399492d579a024ed7520
treea298dde4114bab882127210853c218eac3ab8051
parentccc97432adf50156da86132ad75e3a99c9c0d3eb
clk: socfpga: Add initial Arria10 clock driver

Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
drivers/clk/Makefile
drivers/clk/altera/Makefile [new file with mode: 0644]
drivers/clk/altera/clk-arria10.c [new file with mode: 0644]