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[AArch64] Select SMULL for zero extended vectors when top bit is zero
authorZain Jaffal <z_jaffal@apple.com>
Thu, 8 Dec 2022 06:21:53 +0000 (08:21 +0200)
committerZain Jaffal <z_jaffal@apple.com>
Thu, 8 Dec 2022 07:06:18 +0000 (09:06 +0200)
commitf9e0390751cb5eefbbbc191f851c52422acacab1
tree4e13fa9122f208f76380ae8a5a1ab87f35f45c78tree | snapshot
parent1eab2d699e9581305f32473291e6afa47017d582commit | diff
[AArch64] Select SMULL for zero extended vectors when top bit is zero

we can safely replace a `zext` instruction with `sext` if the top bit is zero. This is useful because we can select `smull` when both operands are sign extended.

Reviewed By: fhahn, dmgreen

Differential Revision: https://reviews.llvm.org/D134711
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/aarch64-smull.ll diff | blob | history
Domain: System / Toolchain;